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authorEric Biederman <ebiederm@xmission.com>2004-10-27 01:18:16 +0000
committerEric Biederman <ebiederm@xmission.com>2004-10-27 01:18:16 +0000
commit3566b3d545dd13f3760e6aa1fc50159243991e1d (patch)
tree2d35076ba899562ce61837e4d272f27537b0dd78 /src/cpu/intel/model_6xx
parenteefdb038981a0fcc93df5c6c934f8138a43873bb (diff)
downloadcoreboot-3566b3d545dd13f3760e6aa1fc50159243991e1d.tar.xz
- Bug fixes to the P-III support
- Initial Pentium-M support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_6xx')
-rw-r--r--src/cpu/intel/model_6xx/model_6xx_init.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c
index 43baf6e346..d33ac58dfd 100644
--- a/src/cpu/intel/model_6xx/model_6xx_init.c
+++ b/src/cpu/intel/model_6xx/model_6xx_init.c
@@ -26,7 +26,7 @@ static uint32_t microcode_updates[] = {
};
-static void model_f0x_init(device_t dev)
+static void model_6xx_init(device_t dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
@@ -40,7 +40,7 @@ static void model_f0x_init(device_t dev)
};
static struct device_operations cpu_dev_ops = {
- .init = model_f0x_init,
+ .init = model_6xx_init,
};
static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_INTEL, 0x0672 },