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authorStefan Reinauer <stepan@coresystems.de>2010-04-27 06:56:47 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-27 06:56:47 +0000
commit14e22779625de673569c7b950ecc2753fb915b31 (patch)
tree14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/cpu/intel/model_f0x
parent0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff)
downloadcoreboot-14e22779625de673569c7b950ecc2753fb915b31.tar.xz
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_f0x')
-rw-r--r--src/cpu/intel/model_f0x/model_f0x_init.c4
-rw-r--r--src/cpu/intel/model_f0x/multiplier.h8
2 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c
index c4d1ef085e..568d4d70ee 100644
--- a/src/cpu/intel/model_f0x/model_f0x_init.c
+++ b/src/cpu/intel/model_f0x/model_f0x_init.c
@@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = {
* microcode update lengths. They are encoded in int 8 and 9. A
* dummy header of nulls must terminate the list.
*/
-
+
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
@@ -32,7 +32,7 @@ static void model_f0x_init(device_t dev)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
-
+
/* Update the microcode */
intel_update_microcode(microcode_updates);
diff --git a/src/cpu/intel/model_f0x/multiplier.h b/src/cpu/intel/model_f0x/multiplier.h
index e2f81362e8..a3b1fcb309 100644
--- a/src/cpu/intel/model_f0x/multiplier.h
+++ b/src/cpu/intel/model_f0x/multiplier.h
@@ -1,5 +1,5 @@
-/*
+/*
** NMI A20M IGNNE INTR
* X8 H H H H
* X9 H H H L projected
@@ -8,7 +8,7 @@
* X12 H L H H
* X13 H L H L
* X14 H L L H
- * X15 H L L L
+ * X15 H L L L
* X16 L H H H
* X17 L H H L
* X18 L H L H
@@ -18,7 +18,7 @@
* X22 L L L H projected
* X23 L L L L projected
*
- ** NMI INTR IGNNE A20M
+ ** NMI INTR IGNNE A20M
* X8 H H H H
* X9 H L H H projected
* X10 H H L H
@@ -26,7 +26,7 @@
* X12 H H H L
* X13 H L H L
* X14 H H L L
- * X15 H L L L
+ * X15 H L L L
* X16 L H H H
* X17 L L H H
* X18 L H L H