summaryrefslogtreecommitdiff
path: root/src/cpu/intel/model_f0x
diff options
context:
space:
mode:
authorAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-12-06 23:14:54 -0600
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2014-01-16 05:34:25 +0100
commit2c38f50b4ad8850676a70427bf1e2e9e9aab82a4 (patch)
tree68fe15f5e270e69ab9810b12fa2bf61d7ff71585 /src/cpu/intel/model_f0x
parentb4c39902edbba61827c60a75fe84e748e217b8be (diff)
downloadcoreboot-2c38f50b4ad8850676a70427bf1e2e9e9aab82a4.tar.xz
cpu/intel: Make all Intel CPUs load microcode from CBFS
The sequence to inject microcode updates is virtually the same for all Intel CPUs. The same function is used to inject the update in both CBFS and hardcoded cases, and in both of these cases, the microcode resides in the ROM. This should be a safe change across the board. The function which loaded compiled-in microcode is also removed here in order to prevent it from being used in the future. The dummy terminators from microcode need to be removed if this change is to work when generating microcode from several microcode_blob.c files, as is the case for older socketed CPUs. Removal of dummy terminators is done in a subsequent patch. Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4495 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_f0x')
-rw-r--r--src/cpu/intel/model_f0x/Kconfig1
-rw-r--r--src/cpu/intel/model_f0x/Makefile.inc2
-rw-r--r--src/cpu/intel/model_f0x/microcode_blob.c14
-rw-r--r--src/cpu/intel/model_f0x/model_f0x_init.c17
4 files changed, 18 insertions, 16 deletions
diff --git a/src/cpu/intel/model_f0x/Kconfig b/src/cpu/intel/model_f0x/Kconfig
index 9dd7fd0bdc..06165890e1 100644
--- a/src/cpu/intel/model_f0x/Kconfig
+++ b/src/cpu/intel/model_f0x/Kconfig
@@ -1,3 +1,4 @@
config CPU_INTEL_MODEL_F0X
bool
select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 79ea2a0632..6c16419947 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1 +1,3 @@
ramstage-y += model_f0x_init.c
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
new file mode 100644
index 0000000000..079a2cb390
--- /dev/null
+++ b/src/cpu/intel/model_f0x/microcode_blob.c
@@ -0,0 +1,14 @@
+/* 256KB cache */
+unsigned microcode_updates_f0x[] = {
+ #include "microcode-678-2f0708.h"
+ #include "microcode-965-m01f0a13.h"
+ #include "microcode-983-m02f0a15.h"
+ #include "microcode-964-m01f0712.h"
+ #include "microcode-966-m04f0a14.h"
+
+ /* Dummy terminator */
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c
index ed12b6edfd..8d8118224e 100644
--- a/src/cpu/intel/model_f0x/model_f0x_init.c
+++ b/src/cpu/intel/model_f0x/model_f0x_init.c
@@ -9,21 +9,6 @@
#include <cpu/intel/microcode.h>
#include <cpu/x86/cache.h>
-/* 256KB cache */
-static uint32_t microcode_updates[] = {
- #include "microcode-678-2f0708.h"
- #include "microcode-965-m01f0a13.h"
- #include "microcode-983-m02f0a15.h"
- #include "microcode-964-m01f0712.h"
- #include "microcode-966-m04f0a14.h"
-
- /* Dummy terminator */
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
-};
-
static void model_f0x_init(device_t dev)
{
/* Turn on caching if we haven't already */
@@ -32,7 +17,7 @@ static void model_f0x_init(device_t dev)
x86_mtrr_check();
/* Update the microcode */
- intel_update_microcode(microcode_updates);
+ intel_update_microcode_from_cbfs();
/* Enable the local cpu apics */
setup_lapic();