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author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 15:15:05 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-23 14:46:36 +0000 |
commit | f26693283655eff7c31275621439f8416eeb3242 (patch) | |
tree | 6c4533fcd186faed76e8805d5fa33b171447f67c /src/cpu/intel/model_f3x/model_f3x_init.c | |
parent | 6336d4c48d2f85629ff668da36711ea794f70ab5 (diff) | |
download | coreboot-f26693283655eff7c31275621439f8416eeb3242.tar.xz |
nb/intel/i945: Use parallel MP init
Use the parallel mp init path to initialize AP's. This should result
in a moderate speedup.
Tested on Intel D945GCLF (1 core 2 threads), still boots fine and is
26ms faster compared to lapic_cpu_init.
This removes the option to disable HT siblings.
Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/cpu/intel/model_f3x/model_f3x_init.c')
-rw-r--r-- | src/cpu/intel/model_f3x/model_f3x_init.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index b71e2797d3..fc0db17a54 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -24,7 +24,7 @@ static void model_f3x_init(struct device *cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); - if (!intel_ht_sibling()) { + if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) { /* MTRRs are shared between threads */ x86_setup_mtrrs(); x86_mtrr_check(); @@ -37,7 +37,8 @@ static void model_f3x_init(struct device *cpu) setup_lapic(); /* Start up my CPU siblings */ - intel_sibling_init(cpu); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { |