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| author | Yinghai Lu <yinghailu@gmail.com> | 2005-07-08 02:49:49 +0000 |
|---|---|---|
| committer | Yinghai Lu <yinghailu@gmail.com> | 2005-07-08 02:49:49 +0000 |
| commit | 13f1c2af8be2cd7f7e99a678f5d428a65b771811 (patch) | |
| tree | 27cad5581f1fa150f573149d48e82f70ba1b1d9f /src/cpu/intel/model_f3x | |
| parent | 14cde9e96a777f9d75016a13b23fab0480515f58 (diff) | |
| download | coreboot-13f1c2af8be2cd7f7e99a678f5d428a65b771811.tar.xz | |
eric patch
1. x86_setup_mtrr take address bit.
2. generic ht, pcix, pcie beidge...
3. scan bus and reset_bus
4. ht read ctrl to decide if the ht chain
is ready
5. Intel e7520 and e7525 support
6. new ich5r support
7. intel sb 6300 support.
yhlu patch
1. split x86_setup_mtrrs to fixed and var
2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
3. in_conherent.c K8_SCAN_PCI_BUS
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_f3x')
| -rw-r--r-- | src/cpu/intel/model_f3x/model_f3x_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index a89e7d1782..20b8518c7c 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -31,7 +31,7 @@ static void model_f3x_init(device_t cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); - x86_setup_mtrrs(); + x86_setup_mtrrs(36); x86_mtrr_check(); /* Update the microcode */ |