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| author | Sven Schnelle <svens@stackframe.org> | 2012-01-10 12:01:43 +0100 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2012-01-10 21:51:40 +0100 |
| commit | adfbcb79ab719af4435e3fdbb8321cda825e076c (patch) | |
| tree | b1a6b834c0c7b50c69a01bd4b969fadc132df472 /src/cpu/intel/model_f3x | |
| parent | 75fb40e15dbffe4148ab108e11d10fe3a9ed6cbe (diff) | |
| download | coreboot-adfbcb79ab719af4435e3fdbb8321cda825e076c.tar.xz | |
MTRR: get physical address size from CPUID
The current code uses static values for the physical address size
supported by a CPU. This isn't always the right value: I.e. on
model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
Xeons from the same family have 38 bits, which results in invalid
MTRR setup. Fix this by getting the right number from CPUID.
Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/529
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_f3x')
| -rw-r--r-- | src/cpu/intel/model_f3x/model_f3x_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index f04ddcc0ce..580c98b4d7 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -31,7 +31,7 @@ static void model_f3x_init(device_t cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); - x86_setup_mtrrs(36); + x86_setup_mtrrs(); x86_mtrr_check(); /* Update the microcode */ |