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author | Keith Hui <buurin@gmail.com> | 2010-03-05 16:18:38 +0000 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-03-05 16:18:38 +0000 |
commit | e1ec158c0a96c2bd51afa73e1bb74d64701264b0 (patch) | |
tree | cc21ff42d716187eb9cdfb89a0a6d255b20d9ab5 /src/cpu/intel/slot_1 | |
parent | ae22bcd6d99174994b5ac5e3369e0154bb9678c3 (diff) | |
download | coreboot-e1ec158c0a96c2bd51afa73e1bb74d64701264b0.tar.xz |
Add proper Slot 1 CPU support code/infrastructure.
Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/slot_1')
-rw-r--r-- | src/cpu/intel/slot_1/Kconfig | 33 | ||||
-rw-r--r-- | src/cpu/intel/slot_1/Makefile.inc | 29 | ||||
-rw-r--r-- | src/cpu/intel/slot_1/chip.h | 24 | ||||
-rw-r--r-- | src/cpu/intel/slot_1/slot_1.c | 26 |
4 files changed, 112 insertions, 0 deletions
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig new file mode 100644 index 0000000000..31eea999a6 --- /dev/null +++ b/src/cpu/intel/slot_1/Kconfig @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Keith Hui <buurin@gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config CPU_INTEL_SLOT_1 + bool + +config DCACHE_RAM_BASE + hex + default 0xc0000 + depends on CPU_INTEL_SLOT_1 + +config DCACHE_RAM_SIZE + hex + default 0x01000 + depends on CPU_INTEL_SLOT_1 + diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc new file mode 100644 index 0000000000..169265664c --- /dev/null +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -0,0 +1,29 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +obj-y += slot_1.o +subdirs-y += ../model_6xx +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode + diff --git a/src/cpu/intel/slot_1/chip.h b/src/cpu/intel/slot_1/chip.h new file mode 100644 index 0000000000..6721d6ee8b --- /dev/null +++ b/src/cpu/intel/slot_1/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Keith Hui <buurin@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_intel_slot_1_ops; + +struct cpu_intel_slot_1_config { +}; diff --git a/src/cpu/intel/slot_1/slot_1.c b/src/cpu/intel/slot_1/slot_1.c new file mode 100644 index 0000000000..548127fbcc --- /dev/null +++ b/src/cpu/intel/slot_1/slot_1.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Keith Hui <buurin@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_intel_slot_1_ops = { + CHIP_NAME("Slot 1 CPU") +}; |