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authorLee Leahy <leroy.p.leahy@intel.com>2017-03-15 18:08:50 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2017-03-16 04:14:09 +0100
commit26eeb0f8ad554b1fa08d58080da8ce2d22081c1c (patch)
tree2b960b57e2175c94a852ca52e1c0db4abd1a69fb /src/cpu/intel/slot_1
parent73a28942031675fce20d6649d2c2ce66fe62f416 (diff)
downloadcoreboot-26eeb0f8ad554b1fa08d58080da8ce2d22081c1c.tar.xz
cpu/intel: Fix brace issues detected by checkpatch.pl
Fix the following error and warning detected by checkpatch.pl: ERROR: that open brace { should be on the previous line WARNING: braces {} are not necessary for single statement blocks TEST=Build and run on Galileo Gen2 Change-Id: Icdd6bd9ae578589b4d42002d200fa8f83920265e Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18849 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/intel/slot_1')
-rw-r--r--src/cpu/intel/slot_1/l2_cache.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c
index 1415a0da4f..b7b9719747 100644
--- a/src/cpu/intel/slot_1/l2_cache.c
+++ b/src/cpu/intel/slot_1/l2_cache.c
@@ -221,9 +221,8 @@ int signal_l2(u32 address, u32 data_high, u32 data_low, int way, u8 command)
/* Write data to BBL_CR_D{0..3} */
msr.lo = data_low;
msr.hi = data_high;
- for (i = BBL_CR_D0; i <= BBL_CR_D3; i++) {
+ for (i = BBL_CR_D0; i <= BBL_CR_D3; i++)
wrmsr(i, msr);
- }
/* Put the command and way into BBL_CR_CTL */
msr = rdmsr(BBL_CR_CTL);
@@ -669,8 +668,7 @@ int p6_configure_l2_cache(void)
printk(BIOS_DEBUG, "write_l2(4, %x)\n", v);
a = read_l2(4);
- if (a >= 0)
- {
+ if (a >= 0) {
a &= 0xfffc;
a |= v;
a = write_l2(4, a);