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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-25 06:03:14 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-17 19:15:28 +0000
commit54d6a288df961255465abf376539ea4a68b8b0f0 (patch)
tree665b95f74484e739fa2fddb5b87c167268e0dbbc /src/cpu/intel/slot_1
parent82112b22a2f06912f0454ed24bf684a6dcdc3696 (diff)
downloadcoreboot-54d6a288df961255465abf376539ea4a68b8b0f0.tar.xz
cpu/intel/slot_1: Switch to different CAR setup
This moves CAR stack under variable MTRRs and removes old CAR code that used complex fixed MTRRs and placed stack in low memory. Change-Id: I75ec842ae3b6771cc3f7ff652adbe386c03b9a5f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/26586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu/intel/slot_1')
-rw-r--r--src/cpu/intel/slot_1/Kconfig2
-rw-r--r--src/cpu/intel/slot_1/Makefile.inc4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index f535a03bf1..ab6663258f 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -28,7 +28,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy
config DCACHE_RAM_BASE
hex
- default 0xce000
+ default 0xfefc0000
config DCACHE_RAM_SIZE
hex
diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc
index ca7c154298..9e34106db2 100644
--- a/src/cpu/intel/slot_1/Makefile.inc
+++ b/src/cpu/intel/slot_1/Makefile.inc
@@ -28,5 +28,5 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
-cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
-romstage-y += ../car/romstage_legacy.c
+cpu_incs-y += $(src)/cpu/intel/car/p3/cache_as_ram.S
+romstage-y += ../car/romstage.c