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authorUwe Hermann <uwe@hermann-uwe.de>2010-10-06 19:32:39 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-10-06 19:32:39 +0000
commit6f2d20ec490a276a087acad0b3866c0f3ee844c4 (patch)
tree8b96891ff7986129f1cee5c556719fd1edc1aa73 /src/cpu/intel/slot_1
parent5225520172a1d1e5c19a93c9178ecd7b72a13248 (diff)
downloadcoreboot-6f2d20ec490a276a087acad0b3866c0f3ee844c4.tar.xz
Convert all Intel 440BX boards to Cache-as-RAM (CAR).
- Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig. - Add the following in src/cpu/intel/slot_1/Makefile.inc: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Remove "select ROMCC" from all 440BX board Kconfig files. - Drop all early_mtrr_init() calls, that's done by CAR code now. Various small fixes were needed to make it build: - Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(), those were never called anyways. - Remove the "static" from the main() functions in romstage.c files. - Always call dump_spd_registers() from the 440BX debug.c, but use "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging is enabled in menuconfig. - Drop all "lib/ramtest.c" #includes and ram_check() calls (even if commented out) from romstage.c's, as we've done for most other boards. - Add missing #includes or prototypes. Some of the prototypes will be removed later when we get rid of the #include'd .c files. Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/slot_1')
-rw-r--r--src/cpu/intel/slot_1/Kconfig1
-rw-r--r--src/cpu/intel/slot_1/Makefile.inc2
2 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index 3639c23bf7..d10de589e7 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -19,6 +19,7 @@
config CPU_INTEL_SLOT_1
bool
+ select CACHE_AS_RAM
config DCACHE_RAM_BASE
hex
diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc
index e51f416dab..1b68ccdabf 100644
--- a/src/cpu/intel/slot_1/Makefile.inc
+++ b/src/cpu/intel/slot_1/Makefile.inc
@@ -27,3 +27,5 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
+cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
+