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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-19 21:48:59 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-21 16:20:30 +0000 |
| commit | 99e0c7ddc1004b69df65483c029ee8915650223a (patch) | |
| tree | 0f90917eb85c669c7d8e5ece7782f73c91c54bd2 /src/cpu/intel/slot_1 | |
| parent | b6265139c7b0e1dfc1706ba896349e59d62a069d (diff) | |
| download | coreboot-99e0c7ddc1004b69df65483c029ee8915650223a.tar.xz | |
src/cpu: Drop unneeded empty lines
Change-Id: I116b15c83fcc5d69d3f80a2e6cf0fb085064d9a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/cpu/intel/slot_1')
| -rw-r--r-- | src/cpu/intel/slot_1/l2_cache.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index ce3634b667..57d1fd4af0 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -189,7 +189,6 @@ int calculate_l2_latency(void) return 0; } - /* Setup address, data_high:data_low into the L2 * control registers and then issue command with correct cache way */ |