summaryrefslogtreecommitdiff
path: root/src/cpu/intel/slot_1
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2016-03-07 16:23:47 -0600
committerAaron Durbin <adurbin@chromium.org>2016-03-08 23:58:01 +0100
commit2a08137feebaf0f8f55feeff00096f5a9d03f44c (patch)
tree269676f6d212e7d02d4069891d629881ccb7b034 /src/cpu/intel/slot_1
parentf5452085979d9031023b1b810abf0493757e6287 (diff)
downloadcoreboot-2a08137feebaf0f8f55feeff00096f5a9d03f44c.tar.xz
x86 chipsets: utilize x86_setup_mtrrs_with_detect()
For all the chipsets which were performing the following sequence: x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); Replace that with x86_setup_mtrrs_with_detect() since it is equivalent. Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13936 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/cpu/intel/slot_1')
0 files changed, 0 insertions, 0 deletions