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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-15 07:47:51 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-15 07:47:51 +0000 |
| commit | af8b2b91b48229d804f1f391e294467cd91adef5 (patch) | |
| tree | 064d85a1664eb0082e3e73ae56842c0dd10c6884 /src/cpu/intel/slot_2 | |
| parent | e49903650cbb8a924a18bcfa28b270f79ef398a1 (diff) | |
| download | coreboot-af8b2b91b48229d804f1f391e294467cd91adef5.tar.xz | |
Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.
This CAR implementation hardcodes the Cache-as-RAM base address to:
0xd0000 - CacheSize
so the DCACHE_RAM_BASE is never actually used for this implementation
and these sockets.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/slot_2')
| -rw-r--r-- | src/cpu/intel/slot_2/Kconfig | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/cpu/intel/slot_2/Kconfig b/src/cpu/intel/slot_2/Kconfig index 49f3cb1d53..2862431f04 100644 --- a/src/cpu/intel/slot_2/Kconfig +++ b/src/cpu/intel/slot_2/Kconfig @@ -20,11 +20,6 @@ config CPU_INTEL_SLOT_2 bool -config DCACHE_RAM_BASE - hex - default 0xc0000 - depends on CPU_INTEL_SLOT_2 - config DCACHE_RAM_SIZE hex default 0x01000 |