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authorArthur Heymans <arthur@aheymans.xyz>2018-02-05 19:08:03 +0100
committerArthur Heymans <arthur@aheymans.xyz>2018-04-10 09:30:21 +0000
commit67031a565b3179fa5a28282fc2e24b47d16003e8 (patch)
treed56eaf320fcdc2b2940a24d77c20077fb970951c /src/cpu/intel/smm
parent64f0bcb6b0c4ee0fb55e6e600a48a1c61d2e97ef (diff)
downloadcoreboot-67031a565b3179fa5a28282fc2e24b47d16003e8.tar.xz
cpu/intel/sandybridge: Put stage cache into TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. The code is mostly copied from src/cpu/intel/haswell. TESTED on Thinkpad X220: on a cold boot the stage cache gets created and on S3 the cached ramstage gets properly used. Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/smm')
-rw-r--r--src/cpu/intel/smm/gen1/smmrelocate.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index da43de09fd..e80fa31489 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -132,6 +132,10 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
params->ied_base = tsegmb + params->smram_size;
params->ied_size = tseg_size - params->smram_size;
+ /* Adjust available SMM handler memory size. */
+ if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM))
+ params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
+
/* SMRR has 32-bits of valid address aligned to 4KiB. */
params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0;