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authorArthur Heymans <arthur@aheymans.xyz>2018-06-03 10:29:07 +0200
committerArthur Heymans <arthur@aheymans.xyz>2018-06-05 07:48:12 +0000
commit7a8205ba353fdf7063791926f82f84c7a9491c35 (patch)
tree95b09652ab9071f2e97008cc804c7df7fd50242e /src/cpu/intel/socket_BGA956
parent711fb811acd403301bb59499071a82ecf112f687 (diff)
downloadcoreboot-7a8205ba353fdf7063791926f82f84c7a9491c35.tar.xz
cpu/intel/car/core2: Prepare for POSTCAR_STAGE support
Split of the model_6ex cache as ram to support POSTCAR_STAGE, which is also needed for future C_ENVIRONMENT_BOOTBLOCK. When using POSTCAR_STAGE the p4-netburst/exit_car.S is using since it is identical. Change-Id: Ibe9f065fdf1d702b73333ea7bb32daca15ba1293 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/intel/socket_BGA956')
-rw-r--r--src/cpu/intel/socket_BGA956/Makefile.inc7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc
index 22c1a7c9eb..f33b409c15 100644
--- a/src/cpu/intel/socket_BGA956/Makefile.inc
+++ b/src/cpu/intel/socket_BGA956/Makefile.inc
@@ -8,6 +8,11 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
-# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
+ifneq ($(CONFIG_POSTCAR_STAGE),y)
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+else
+cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
+postcar-y += ../car/p4-netburst/exit_car.S
+endif
+
romstage-y += ../car/romstage.c