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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-09 17:43:27 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-18 20:52:01 +0100 |
| commit | c86c6b33e8ca32ffa0f0d7e30f35f1fb31fe3b4a (patch) | |
| tree | 12171a9fa9d44cc55363defd7a6388ca3a10a898 /src/cpu/intel/socket_BGA956 | |
| parent | c3e0389c058ea097e80d6d95434b56b6edff8389 (diff) | |
| download | coreboot-c86c6b33e8ca32ffa0f0d7e30f35f1fb31fe3b4a.tar.xz | |
intel cache-as-ram: Move DCACHE_RAM_BASE
Having same memory region set as both WRPROT and WRBACK
using MTRRs is undefined behaviour. This could happen if
we allow DCACHE_RAM_BASE to be located within CBFS in SPI
flash memory and XIP romstage is at the same location.
As SPI master by default decodes all of top 16MiB below
4GiB, initial cache-as-ram line fills may have actually
read from SPI flash even in the case DCACHE_RAM_BASE was
below the nominal 4GiB - ROM_SIZE.
There are no reasons to have this as board-specific setting.
Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/socket_BGA956')
| -rw-r--r-- | src/cpu/intel/socket_BGA956/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 4dd5a60528..6c5e414029 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -8,7 +8,7 @@ if CPU_INTEL_SOCKET_BGA956 config DCACHE_RAM_BASE hex - default 0xffaf8000 + default 0xfefc0000 config DCACHE_RAM_SIZE hex |