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| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-02 22:23:11 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-09-04 15:09:32 +0000 |
| commit | 439356fabcacbbc3a3231f6e27b5298f8f5ad41f (patch) | |
| tree | 82e94a01f5a59b1d495db0e6225556bbbd0edfb0 /src/cpu/intel/socket_BGA956 | |
| parent | bc98cc66b2fe787173ec04b84ea11bc3e57fe373 (diff) | |
| download | coreboot-439356fabcacbbc3a3231f6e27b5298f8f5ad41f.tar.xz | |
x86: remove cpu_incs as romstage Make variable
When building up which files to include in romstage there
were both 'cpu_incs' and 'cpu_incs-y' which were used to
generate crt0.S. Remove the former to settle on cpu_incs-y
as the way to be included.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi. No include file changes.
Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/intel/socket_BGA956')
| -rw-r--r-- | src/cpu/intel/socket_BGA956/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index 601997241d..2325bb9e32 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -9,4 +9,4 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep # Use Intel Core (not Core 2) code for CAR init, any CPU might be used. -cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc |