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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-03 10:44:55 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-05 07:49:09 +0000 |
| commit | aa7cf5597b0f4d59c5d7fe42a8b5130852056bff (patch) | |
| tree | e7bcbf378dcca3971be89d8e916b1e111cc4a089 /src/cpu/intel/socket_FCBGA559 | |
| parent | 2dcc3a5c68b4bacbe96c1543cc20e5a3425889fb (diff) | |
| download | coreboot-aa7cf5597b0f4d59c5d7fe42a8b5130852056bff.tar.xz | |
nb/intel/pineview: Switch to POSTCAR_STAGE
Change-Id: If23925e2837645c974e4094e7e2d90e700d3d9e8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/intel/socket_FCBGA559')
| -rw-r--r-- | src/cpu/intel/socket_FCBGA559/Makefile.inc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 7c37019194..7993294a17 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -8,10 +8,7 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -ifneq ($(CONFIG_POSTCAR_STAGE),y) -cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc -else cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S postcar-y += ../car/p4-netburst/exit_car.S -endif + romstage-y += ../car/romstage.c |