diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-22 16:33:24 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-30 10:21:43 +0100 |
| commit | 773485b8920145443da8b09712553c10c954fed1 (patch) | |
| tree | fff1c5eec6b6b7782da4d9d8c0afa3492bd583a8 /src/cpu/intel/socket_FC_PGA370 | |
| parent | 2b9814629b4b7d96340033fc38c5003e6a8db93e (diff) | |
| download | coreboot-773485b8920145443da8b09712553c10c954fed1.tar.xz | |
intel CAR: Fix DCACHE_RAM_BASE for old sockets
When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored
and was not correctly set on affected sockets and boards. It was still
referenced in romstage linker script. This was discovered by clang builds
failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed.
The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken
from intel/cpu/cache_as_ram.inc.
Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7887
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/cpu/intel/socket_FC_PGA370')
| -rw-r--r-- | src/cpu/intel/socket_FC_PGA370/Kconfig | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/cpu/intel/socket_FC_PGA370/Kconfig b/src/cpu/intel/socket_FC_PGA370/Kconfig index f8ea0f96e8..91295b1517 100644 --- a/src/cpu/intel/socket_FC_PGA370/Kconfig +++ b/src/cpu/intel/socket_FC_PGA370/Kconfig @@ -24,7 +24,14 @@ config CPU_INTEL_SOCKET_FC_PGA370 select MMX select SSE +if CPU_INTEL_SOCKET_FC_PGA370 + +config DCACHE_RAM_BASE + hex + default 0xc8000 + config DCACHE_RAM_SIZE hex - default 0x8000 - depends on CPU_INTEL_SOCKET_FC_PGA370 + default 0x08000 + +endif |