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authorPaul Menzel <paulepanter@users.sourceforge.net>2013-02-23 00:15:49 +0100
committerMarc Jones <marc.jones@se-eng.com>2013-03-07 00:45:41 +0100
commite988b515f11fa9483fc5209a9894b8d485525a61 (patch)
treec732273dbe9dd9cd5baa79225d2da7ad9a985873 /src/cpu/intel/socket_LGA775
parent6bde149d9c56a824eff5db7bb06d7c386fb2be30 (diff)
downloadcoreboot-e988b515f11fa9483fc5209a9894b8d485525a61.tar.xz
ASRock E350M1: Let `BiosGnbPcieSlotReset()` return `AGESA_UNSUPPORTED`
Quoting Jens Rottmann [1]: Nevertheless I still think this whole function is bogus for the E350M1. The function assumes GPIO21 is wired to reset APU PCIe lane 0+1 (PCIe x8, port 4+5 as Coreboot/AGESA calls it), GPIO25 resets lane 2 (PCIe x4) and GPIO02 lane 3. But the E350M1 has PCIe x16 i.e. probably APU lanes 0-3 bundled, completely different layout. They could have chosen GPIO21 to force resets, or 25 - or maybe 50 like on the Persimmon or any other they fancied or - and this is the most probable - none at all. Having BiosGnbPcieSlotReset() toggle some GPIOs without knowing what they do on the E350M1 (if anything at all) is nonsense. In my opinion this whole function should just "return AGESA_UNSUPPORTED" and good riddance. [1] http://review.coreboot.org/#/c/2445/ Change-Id: Iac66da41182e838c7e6925250cc3982adbb3e4ec Reported-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2489 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Diffstat (limited to 'src/cpu/intel/socket_LGA775')
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