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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-13 08:21:44 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-13 08:21:44 +0000 |
| commit | ab50d62ea6867712eca79e9f0770d6ac35f72ce1 (patch) | |
| tree | 0484728745bb1699e3e4fd2a8f623d508e502661 /src/cpu/intel/socket_PGA370/Kconfig | |
| parent | 51eafdeae621f1b04db51c3b4a690fa993aa48a0 (diff) | |
| download | coreboot-ab50d62ea6867712eca79e9f0770d6ac35f72ce1.tar.xz | |
Convert all Intel i810 boards to CAR.
- Drop "select ROMCC" from the boards, as well as early_mtrr stuff.
- Add "select CACHE_AS_RAM" to socket_PGA370/Kconfig, as well as the
usual DCACHE_RAM_BASE and DCACHE_RAM_SIZE variables.
- In socket_PGA370/Makefile.inc add:
cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
- Other smaller related fixes.
Abuild-tested and boot-tested on MSI MS-6178.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/socket_PGA370/Kconfig')
| -rw-r--r-- | src/cpu/intel/socket_PGA370/Kconfig | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig index 1805e6a294..bfabfb8471 100644 --- a/src/cpu/intel/socket_PGA370/Kconfig +++ b/src/cpu/intel/socket_PGA370/Kconfig @@ -21,10 +21,22 @@ config CPU_INTEL_SOCKET_PGA370 bool select MMX select UDELAY_TSC + select CACHE_AS_RAM + +if CPU_INTEL_SOCKET_PGA370 # Not all CPUs for Socket 370 can do SSE2 config SSE2 bool default n - depends on CPU_INTEL_SOCKET_PGA370 + +config DCACHE_RAM_BASE + hex + default 0xc0000 + +config DCACHE_RAM_SIZE + hex + default 0x01000 + +endif |