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authorArthur Heymans <arthur@aheymans.xyz>2018-01-06 18:40:23 +0100
committerMartin Roth <martinroth@google.com>2018-01-17 17:09:13 +0000
commit0a4e0fd913006de8f5d0a4ea24e013f30243cf5c (patch)
tree47d8e59bd239a7b6b74d25393f9e3efe6cf1e223 /src/cpu/intel/speedstep
parent30bba281b9b4330f5fadf36d187c2512f94c29e0 (diff)
downloadcoreboot-0a4e0fd913006de8f5d0a4ea24e013f30243cf5c.tar.xz
cpu/intel/speedstep: Fix the PNOT ACPI method
The PNOT method never notifies the CPU to update it's _CST methods due to reliance on inexisting variable (PDCx). Add a method in the speedstep ssdt generator to notify all available CPU nodes and hook this up in this file. The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now relies on code generated in the speedstep ssdt generator. CPUs not using the speedstep code never included this PNOT method so this is a logical place for this code to be. Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/speedstep')
-rw-r--r--src/cpu/intel/speedstep/acpi.c13
-rw-r--r--src/cpu/intel/speedstep/acpi/cpu.asl31
2 files changed, 44 insertions, 0 deletions
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index c154da0c29..73b7431608 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -23,6 +23,7 @@
#include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h>
#include <device/device.h>
+#include <string.h>
static int determine_total_number_of_cores(void)
{
@@ -164,4 +165,16 @@ void generate_cpu_entries(device_t device)
/* PPKG is usually used for thermal management
of the first and only package. */
acpigen_write_processor_package("PPKG", 0, cores_per_package);
+
+ /* Add a method to notify processor nodes */
+ acpigen_write_method("\\_PR.CNOT", 1);
+ for (coreID = 0; coreID < cores_per_package; coreID++) {
+ char buffer[DEVICE_PATH_MAX];
+ snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c",
+ '0' + coreID / 10, '0' + coreID % 10);
+ acpigen_emit_byte(NOTIFY_OP);
+ acpigen_emit_namestring(buffer);
+ acpigen_emit_byte(ARG0_OP);
+ }
+ acpigen_pop_len();
}
diff --git a/src/cpu/intel/speedstep/acpi/cpu.asl b/src/cpu/intel/speedstep/acpi/cpu.asl
new file mode 100644
index 0000000000..9ff3f76727
--- /dev/null
+++ b/src/cpu/intel/speedstep/acpi/cpu.asl
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* These come from the dynamically created CPU SSDT */
+External (\_PR.CNOT, MethodObj)
+External (\_PR_.CP00, DeviceObj)
+External (\_PR_.CP00._PPC)
+External (\_PR_.CP01._PPC)
+
+Method (PNOT)
+{
+ If (MPEN) {
+ \_PR.CNOT (0x80) // _PPC
+ Sleep(100)
+ \_PR.CNOT (0x81) // _CST
+ } Else { // UP
+ Notify (\_PR_.CP00, 0x80)
+ Sleep(0x64)
+ Notify(\_PR_.CP00, 0x81)
+ }
+}