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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-01 19:44:56 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-04 05:33:04 +0200 |
| commit | 2765a893ca355caaf7d859e2bff5eb58630e2ddb (patch) | |
| tree | 80ca397f44651f9bda94ff891746f89b23013ee6 /src/cpu/intel | |
| parent | d1cab6650261a2e6e75ff85b1868d723f1e1cc79 (diff) | |
| download | coreboot-2765a893ca355caaf7d859e2bff5eb58630e2ddb.tar.xz | |
src/cpu: Improve code formatting
Change-Id: I17d5efe382da5301a9f5d595186d0fb7576725ca
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16391
Tested-by: build bot (Jenkins)
Reviewed-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-by: Antonello Dettori <dev@dettori.io>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram_ht.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/model_6fx_init.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 3e2b3e24ac..024133b864 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -200,7 +200,7 @@ ap_init: post_code(0x27) /* Do not disable cache (so BSP can enable it). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 18160adfad..67a7408814 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -72,7 +72,7 @@ static void configure_c_states(void) msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo |= (1 << 3); // Dynamic L2 - /* Number of supported C-States */ + /* Number of supported C-States */ msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 |