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authorUwe Hermann <uwe@hermann-uwe.de>2010-10-15 07:47:51 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-10-15 07:47:51 +0000
commitaf8b2b91b48229d804f1f391e294467cd91adef5 (patch)
tree064d85a1664eb0082e3e73ae56842c0dd10c6884 /src/cpu/intel
parente49903650cbb8a924a18bcfa28b270f79ef398a1 (diff)
downloadcoreboot-af8b2b91b48229d804f1f391e294467cd91adef5.tar.xz
Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.
This CAR implementation hardcodes the Cache-as-RAM base address to: 0xd0000 - CacheSize so the DCACHE_RAM_BASE is never actually used for this implementation and these sockets. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/slot_1/Kconfig5
-rw-r--r--src/cpu/intel/slot_2/Kconfig5
-rw-r--r--src/cpu/intel/socket_FC_PGA370/Kconfig5
-rw-r--r--src/cpu/intel/socket_PGA370/Kconfig4
4 files changed, 0 insertions, 19 deletions
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index d10de589e7..45c94ac6f0 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -21,11 +21,6 @@ config CPU_INTEL_SLOT_1
bool
select CACHE_AS_RAM
-config DCACHE_RAM_BASE
- hex
- default 0xc0000
- depends on CPU_INTEL_SLOT_1
-
config DCACHE_RAM_SIZE
hex
default 0x01000
diff --git a/src/cpu/intel/slot_2/Kconfig b/src/cpu/intel/slot_2/Kconfig
index 49f3cb1d53..2862431f04 100644
--- a/src/cpu/intel/slot_2/Kconfig
+++ b/src/cpu/intel/slot_2/Kconfig
@@ -20,11 +20,6 @@
config CPU_INTEL_SLOT_2
bool
-config DCACHE_RAM_BASE
- hex
- default 0xc0000
- depends on CPU_INTEL_SLOT_2
-
config DCACHE_RAM_SIZE
hex
default 0x01000
diff --git a/src/cpu/intel/socket_FC_PGA370/Kconfig b/src/cpu/intel/socket_FC_PGA370/Kconfig
index f3987783a8..88541a8379 100644
--- a/src/cpu/intel/socket_FC_PGA370/Kconfig
+++ b/src/cpu/intel/socket_FC_PGA370/Kconfig
@@ -26,11 +26,6 @@ config CPU_INTEL_SOCKET_FC_PGA370
select CACHE_AS_RAM
select TINY_BOOTBLOCK
-config DCACHE_RAM_BASE
- hex
- default 0xffdf8000
- depends on CPU_INTEL_SOCKET_FC_PGA370
-
config DCACHE_RAM_SIZE
hex
default 0x8000
diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig
index bfabfb8471..adfb5f3a73 100644
--- a/src/cpu/intel/socket_PGA370/Kconfig
+++ b/src/cpu/intel/socket_PGA370/Kconfig
@@ -30,10 +30,6 @@ config SSE2
bool
default n
-config DCACHE_RAM_BASE
- hex
- default 0xc0000
-
config DCACHE_RAM_SIZE
hex
default 0x01000