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| author | Alexander Couzens <lynxis@fe80.eu> | 2015-01-28 01:51:04 +0100 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2015-02-11 02:58:06 +0100 |
| commit | f251a6d7d48d9ae91d4cce7195952395762e07a8 (patch) | |
| tree | 46bfb6fa03d4db3ccb8776731768b4d2e3c34aee /src/cpu/intel | |
| parent | c768f9231b4237652c7e91a524194847ae140b5a (diff) | |
| download | coreboot-f251a6d7d48d9ae91d4cce7195952395762e07a8.tar.xz | |
cpu/intel: >= nehalem: add comments to msr finalize's
Improve documentation of lock down MSRs in finalize().
Most of these aren't documented in public MSRs.
Change-Id: I4fc47bb9b71bdd7907aae65fc18b419a17ae8547
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8294
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/fsp_model_206ax/finalize.c | 9 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/finalize.c | 9 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/finalize.c | 10 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/finalize.c | 9 |
4 files changed, 36 insertions, 1 deletions
diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c index 4ed5d1e5f8..534b1578c9 100644 --- a/src/cpu/intel/fsp_model_206ax/finalize.c +++ b/src/cpu/intel/fsp_model_206ax/finalize.c @@ -24,6 +24,11 @@ #include <cpu/x86/msr.h> #include "model_206ax.h" +/* MSR Documentation based on + * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)" + * Document Number 504790 + * Revision 1.6.0, June 2012 */ + static void msr_set_bit(unsigned reg, unsigned bit) { msr_t msr = rdmsr(reg); @@ -43,6 +48,7 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_model_206ax_finalize_smm(void) { + /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ @@ -67,6 +73,9 @@ void intel_model_206ax_finalize_smm(void) msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif + /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); + + /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); } diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index 1731322d83..b87e8c2b3e 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -24,6 +24,11 @@ #include <cpu/x86/msr.h> #include "haswell.h" +/* MSR Documentation based on + * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)" + * Document Number 504790 + * Revision 1.6.0, June 2012 */ + #if 0 static void msr_set_bit(unsigned reg, unsigned bit) { @@ -46,6 +51,7 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_cpu_haswell_finalize_smm(void) { #if 0 + /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ @@ -70,7 +76,10 @@ void intel_cpu_haswell_finalize_smm(void) msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif + /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); + + /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); #endif } diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index b37a84cfe7..1835dce3db 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -25,6 +25,11 @@ #include <cpu/intel/speedstep.h> #include "model_2065x.h" +/* MSR Documentation based on + * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)" + * Document Number 504790 + * Revision 1.6.0, June 2012 */ + static void msr_set_bit(unsigned reg, unsigned bit) { msr_t msr = rdmsr(reg); @@ -44,6 +49,7 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_model_2065x_finalize_smm(void) { + /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ @@ -67,7 +73,9 @@ void intel_model_2065x_finalize_smm(void) msr_set_bit(MSR_PP0_POWER_LIMIT, 31); msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif - + /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); + + /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); } diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 2c215a4daf..0c1fe75ba7 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -25,6 +25,11 @@ #include <cpu/intel/speedstep.h> #include "model_206ax.h" +/* MSR Documentation based on + * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)" + * Document Number 504790 + * Revision 1.6.0, June 2012 */ + static void msr_set_bit(unsigned reg, unsigned bit) { msr_t msr = rdmsr(reg); @@ -44,6 +49,7 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_model_206ax_finalize_smm(void) { + /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ @@ -68,6 +74,9 @@ void intel_model_206ax_finalize_smm(void) msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif + /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); + + /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); } |