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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-09-30 21:22:40 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-09-30 21:22:40 +0000 |
| commit | 1d36d6df7dafea5a6f9dec80f4a3998470d440a2 (patch) | |
| tree | dd63064198bf6914420ab2b6c533d7578409d84c /src/cpu/intel | |
| parent | 8463dd9db0dc2ce02423775d0eb62e28aa01e9f9 (diff) | |
| download | coreboot-1d36d6df7dafea5a6f9dec80f4a3998470d440a2.tar.xz | |
Use existing, readable MTRR #defines instead of hardcoding numbers.
Replace $0x200 with $MTRRphysBase_MSR(0) etc. Also, move some #ifdef stuff
a little bit around (should not affect any functionality) to make the
Intel/AMD/VIA CAR implementations more similar and easier to compare.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 105f920b13..0cf5a2e669 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -196,11 +196,13 @@ clear_fixed_var_mtrr_out: wrmsr #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) + #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif + /* enable write base caching so we can do execute in place * on the flash rom. */ |