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| author | Matt DeVillier <matt.devillier@gmail.com> | 2016-09-02 13:29:17 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-16 16:08:24 +0200 |
| commit | 5aaa8ce21c85a41c313c18ca7a4e41a25ab711d9 (patch) | |
| tree | 9978466f54e34641cc94a428cad2a4f56abd9ca8 /src/cpu/intel | |
| parent | f739e7f56a237556240a46ade476f75ed41d4fc1 (diff) | |
| download | coreboot-5aaa8ce21c85a41c313c18ca7a4e41a25ab711d9.tar.xz | |
haswell: add CBMEM_MEMINFO table when initing RAM
Populate a memory_info struct with PEI and SPD data,
in order to inject the CBMEM_INFO table necessary to
populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older
Haswell MRC binary doesn't populate the pei_data struct with
all the info needed, so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index c6765c757c..ac45ee62ad 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -245,6 +245,8 @@ void romstage_common(const struct romstage_params *params) #endif } + setup_sdram_meminfo(params->pei_data); + romstage_handoff_init(wake_from_s3); post_code(0x3f); |