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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-19 20:38:41 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-22 11:03:42 +0200 |
| commit | 65cc526f6f47755b4492cd9fc2134fb2dd067e90 (patch) | |
| tree | 9b7357287b96f73a762592ccc8b7d2153eff1d46 /src/cpu/intel | |
| parent | c5400efc11e181caf0babaa6001de18e3f23c6af (diff) | |
| download | coreboot-65cc526f6f47755b4492cd9fc2134fb2dd067e90.tar.xz | |
Ignore RAMTOP for MTRRs
Without RELOCATABLE_RAMSTAGE have WB cache large enough
to cover the greatest ramstage needs, as there is no benefit
of trying to accurately match the actual need. Choose
this to be bottom 16MiB.
With RELOCATABLE_RAMSTAGE write-back cache of low ram is
only useful for bottom 1MiB of RAM as a small part of this gets used
during SMP initialisation before proper MTRR setup.
Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15249
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram_ht.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 4 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 2 |
5 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 1e21d9dc6d..095b9b6cda 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -388,7 +388,7 @@ no_msr_11e: wrmsr movl $MTRR_PHYS_MASK(0), %ecx rdmsr - movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr #if CACHE_ROM_SIZE diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index b8ce5d6d43..0e8fd09837 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -119,9 +119,9 @@ static void *setup_romstage_stack_after_car(void) slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); num_mtrrs++; - /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push(slot, 0); /* upper base */ slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); num_mtrrs++; diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 51af5c69d2..e6d95d572a 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -233,7 +233,7 @@ before_romstage: xorl %edx, %edx wrmsr movl $MTRR_PHYS_MASK(0), %ecx - movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx // 36bit address space wrmsr diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 0dc3cab1dd..a1f5cc9d80 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -243,7 +243,7 @@ before_romstage: xorl %edx, %edx wrmsr movl $MTRR_PHYS_MASK(0), %ecx - movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx // 36bit address space wrmsr diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 79383e163f..6b80e7ae7b 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -182,7 +182,7 @@ clear_mtrrs: xorl %edx, %edx wrmsr movl $MTRR_PHYS_MASK(0), %ecx - movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr |