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| author | Aaron Durbin <adurbin@chromium.org> | 2013-02-15 15:08:37 -0600 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-21 22:58:17 +0100 |
| commit | 67481ddc2e53cd3420fa8c723edb4fe47dccc196 (patch) | |
| tree | 11be0e451c9c208e0e97d63863efb72e88aad59a /src/cpu/intel | |
| parent | 8584b223fe1a0c9da9a94e28b135cfc7414601dc (diff) | |
| download | coreboot-67481ddc2e53cd3420fa8c723edb4fe47dccc196.tar.xz | |
haswell: set TSEG as WB cacheable in romstage
The TSEG region is accessible until the SMM handler is relocated
to that region. Set the region as cacheable in romstage so that it
can be used for other purposes with fast access.
Change-Id: I92b83896e40bc26a54c2930e05c02492918e0874
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2803
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index ac0e848c7d..b26cbde605 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -82,6 +82,7 @@ static void *setup_romstage_stack_after_car(void) int num_mtrrs; u32 *slot; u32 mtrr_mask_upper; + u32 top_of_ram; /* Top of stack needs to be aligned to a 4-byte boundary. */ top_of_stack = choose_top_of_stack() & ~3; @@ -120,6 +121,7 @@ static void *setup_romstage_stack_after_car(void) slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); num_mtrrs++; + top_of_ram = get_top_of_ram(); /* Cache 8MiB below the top of ram. On haswell systems the top of * ram under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later @@ -127,8 +129,18 @@ static void *setup_romstage_stack_after_car(void) slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, - (get_top_of_ram() - (8 << 20)) | MTRR_TYPE_WRBACK); + slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); + num_mtrrs++; + + /* Cache 8MiB at the top of ram. Top of ram on haswell systems + * is where the TSEG region resides. However, it is not restricted + * to SMM mode until SMM has been relocated. By setting the region + * to cacheable it provides faster access when relocating the SMM + * handler as well as using the TSEG region for other purposes. */ + slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); + slot = stack_push(slot, 0); /* upper base */ + slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); num_mtrrs++; /* Save the number of MTTRs to setup. Return the stack location |