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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2020-07-26 14:23:37 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:31:40 +0000 |
| commit | b01ac7e26453677318776885d4ab870f59553ae6 (patch) | |
| tree | 8cc66d66f6135a56c857c86397caa6e35e856096 /src/cpu/intel | |
| parent | 44cfde02d5d694a6f0eced12333d2350acb498d1 (diff) | |
| download | coreboot-b01ac7e26453677318776885d4ab870f59553ae6.tar.xz | |
cpu/intel/common: Fill cpu voltage in SMBIOS tables
Introduce a weak function to let the platform code provide the processor
voltage in 100mV units.
Implement the function on Intel platforms using the MSR_PERF_STATUS msr.
On other platforms the processor voltage still reads as unknown.
Tested on Intel CFL. The CPU voltage is correctly advertised.
Change-Id: I31a7efcbeede50d986a1c096a4a59a316e09f825
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/common/Kconfig | 3 | ||||
| -rw-r--r-- | src/cpu/intel/common/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/common/voltage.c | 12 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/Kconfig | 1 |
4 files changed, 17 insertions, 0 deletions
diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 01f2721b59..7f9033cf65 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -32,6 +32,9 @@ config CPU_INTEL_COMMON_TIMEBASE endif +config CPU_INTEL_COMMON_VOLTAGE + bool + config CPU_INTEL_COMMON_SMM bool default y if CPU_INTEL_COMMON diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index 8b81a121d3..530ecee009 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,5 +1,6 @@ ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c ramstage-$(CONFIG_CPU_INTEL_COMMON) += hyperthreading.c +ramstage-$(CONFIG_CPU_INTEL_COMMON_VOLTAGE) += voltage.c ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y) bootblock-y += fsb.c diff --git a/src/cpu/intel/common/voltage.c b/src/cpu/intel/common/voltage.c new file mode 100644 index 0000000000..38951a06db --- /dev/null +++ b/src/cpu/intel/common/voltage.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/msr.h> +#include <smbios.h> + +/* This is not an architectural MSR. */ +#define MSR_PERF_STATUS 0x198 + +unsigned int smbios_cpu_get_voltage(void) +{ + return (rdmsr(MSR_PERF_STATUS).hi & 0xffff) * 10 / 8192; +} diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index fbfa71456b..0d3d132006 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select HAVE_ASAN_IN_ROMSTAGE + select CPU_INTEL_COMMON_VOLTAGE config SMM_TSEG_SIZE hex |