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authorPatrick Rudolph <siro@das-labor.org>2017-06-06 10:44:29 +0200
committerMartin Roth <martinroth@google.com>2017-06-09 16:27:19 +0200
commitb9959e279c40b6db50efa61d20838757080fa4dd (patch)
tree2076a6f8bbc9019c555a598d2a3bd5424e3462a0 /src/cpu/intel
parent21e7424fc985f2f92ee7e9f505acd72c53035531 (diff)
downloadcoreboot-b9959e279c40b6db50efa61d20838757080fa4dd.tar.xz
cpu/intel/model_206ax: Use tsc monotonic timer
Switch from lapic to tsc. Allows timestamps to be used in coreboot, as there's a reference clock available to calculate correct time units. Clean Kconfig, remove duplicated lapic code and include tsc dir for LGA1155 boards. Tested on Lenovo T430. Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/model_206ax/Kconfig5
-rw-r--r--src/cpu/intel/model_206ax/Makefile.inc4
-rw-r--r--src/cpu/intel/model_206ax/tsc_freq.c27
-rw-r--r--src/cpu/intel/socket_LGA1155/Makefile.inc1
4 files changed, 35 insertions, 2 deletions
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 6c04fba829..f16b11962c 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -14,12 +14,13 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
- select UDELAY_LAPIC
+ select UDELAY_TSC
+ select TSC_CONSTANT_RATE
+ select TSC_MONOTONIC_TIMER
select SMM_TSEG
select SUPPORT_CPU_UCODE_IN_CBFS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
- select LAPIC_MONOTONIC_TIMER
select CPU_INTEL_COMMON
config BOOTBLOCK_CPU_INIT
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index b79ccd71ff..7516e9d246 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -5,6 +5,10 @@ subdirs-y += ../common
ramstage-y += acpi.c
+ramstage-y += tsc_freq.c
+romstage-y += tsc_freq.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
+
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
diff --git a/src/cpu/intel/model_206ax/tsc_freq.c b/src/cpu/intel/model_206ax/tsc_freq.c
new file mode 100644
index 0000000000..545ca5f106
--- /dev/null
+++ b/src/cpu/intel/model_206ax/tsc_freq.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include "model_206ax.h"
+
+unsigned long tsc_freq_mhz(void)
+{
+ msr_t platform_info;
+
+ platform_info = rdmsr(MSR_PLATFORM_INFO);
+ return SANDYBRIDGE_BCLK * ((platform_info.lo >> 8) & 0xff);
+}
diff --git a/src/cpu/intel/socket_LGA1155/Makefile.inc b/src/cpu/intel/socket_LGA1155/Makefile.inc
index eb7abf065e..539f285d92 100644
--- a/src/cpu/intel/socket_LGA1155/Makefile.inc
+++ b/src/cpu/intel/socket_LGA1155/Makefile.inc
@@ -1,3 +1,4 @@
+subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache