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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-16 14:19:37 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-02-27 09:46:29 +0000 |
| commit | d2d2aef6a3222af909183fb96dc7bc908fac3cd4 (patch) | |
| tree | ff01f96984d46138bf3ab0bb253f04024d9fb0e1 /src/cpu/intel | |
| parent | 5fd1d5ad1258407ade7fe8f72672c878bdfd8f05 (diff) | |
| download | coreboot-d2d2aef6a3222af909183fb96dc7bc908fac3cd4.tar.xz | |
sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location
Many generations of Intel hardware have identical code concerning the
RCBA.
Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/model_2065x/bootblock.c | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/bootblock.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c index ed528d1bdd..edc2996f05 100644 --- a/src/cpu/intel/model_2065x/bootblock.c +++ b/src/cpu/intel/model_2065x/bootblock.c @@ -24,6 +24,7 @@ #include <cpu/intel/microcode/microcode.c> #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK) +#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/ibexpeak/pch.h> #include "model_2065x.h" #else diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 670b09750e..90215a496d 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -28,6 +28,7 @@ IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216) /* Needed for RCBA access to set Soft Reset Data register */ #include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/rcba.h> #else #error "CPU must be paired with Intel BD82X6X or C216 southbridge" #endif |