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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-01 09:50:32 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-01 09:50:32 +0000 |
| commit | 0c781b2694b2c137d9761704954ea38be5ba8a15 (patch) | |
| tree | 55c8bb4ea9f5875da7e4f7ffa6b5e7d2aa87a4b8 /src/cpu/intel | |
| parent | 84b685af5f1e1cf49c2c2f22ae80a8a0df8472f8 (diff) | |
| download | coreboot-0c781b2694b2c137d9761704954ea38be5ba8a15.tar.xz | |
-Â get rid of ASM_CONSOLE_LOGLEVEL except in two assembler files.
- start naming all versions of post code output "post_code()"
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/model_106cx/cache_as_ram.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram.inc | 1 |
3 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index 4781b0521c..da42d4dc66 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -20,7 +20,6 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -#define post_code(x) intel_chip_post_macro(x) #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 848c84d2c2..ad0567e102 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -20,7 +20,6 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -#define post_code(x) intel_chip_post_macro(x) #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 50f9608dcc..b902b1dbf6 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -20,7 +20,6 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -#define post_code(x) intel_chip_post_macro(x) #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> |