haswell: Put each logical processor in its own P-state domain

The recommendation from Intel is to report each core as a
separate logical domain in the _PSD table.

This goes against the recommendation in the ACPI specification
because all of these cores are on the same package and share a
VR so they will do voltage transitions together.

The reasoning is that with a larger number of logical processors
the P-state often ramps too quickly resulting in higher power
consumption.  By exposing each core as a separate domain the OS
can manage them individually allowing the socket to select the
optimum frequency.

$ cat /sys/firmware/acpi/tables/SSDT > /tmp/SSDT
$ iasl -d /tmp/SSDT

Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000000,
      0x000000FE,
      0x00000001
    }
  })
}

Processor (\_PR.CPU1, 0x01, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000001,
      0x000000FE,
      0x00000001
    }
  })
}

Processor (\_PR.CPU2, 0x02, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000002,
      0x000000FE,
      0x00000001
    }
  })
}

Processor (\_PR.CPU3, 0x03, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000003,
      0x000000FE,
      0x00000001
    }
  })
}

Change-Id: I5ef41b6ead4d88e9ba117003293dbc629c376803
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48662
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4130
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
index a4d9cd9292..9e10c7527a 100644
--- a/src/cpu/intel/haswell/acpi.c
+++ b/src/cpu/intel/haswell/acpi.c
@@ -254,7 +254,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
 	len += acpigen_write_PPC_NVS();
 
 	/* Write PSD indicating configured coordination type */
-	len += acpigen_write_PSD_package(core, cores_per_package, coord_type);
+	len += acpigen_write_PSD_package(core, 1, coord_type);
 
 	/* Add P-state entries in _PSS table */
 	len += acpigen_write_name("_PSS");
@@ -346,7 +346,7 @@ void generate_cpu_entries(void)
 
 			/* Generate P-state tables */
 			len_pr += generate_P_state_entries(
-				cpuID-1, cores_per_package);
+				coreID-1, cores_per_package);
 
 			/* Generate C-state tables */
 			len_pr += generate_C_state_entries();