diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-02 20:51:29 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-02 20:51:29 +0000 |
| commit | 36455aade46a1ca44aa1387e1785e72519f7b82d (patch) | |
| tree | 73dfa0ff9ec8fcac0b45ec4cb4f6d81684d07413 /src/cpu/intel | |
| parent | ae3f2b3706b3655627fdaee897d28ac4b5fe2659 (diff) | |
| download | coreboot-36455aade46a1ca44aa1387e1785e72519f7b82d.tar.xz | |
Add comments to make it clear why these two lines are written like that:
movl $REAL_XIP_ROM_BASE, %eax
orl $MTRR_TYPE_WRBACK, %eax
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram.inc | 5 | ||||
| -rw-r--r-- | src/cpu/intel/model_106cx/cache_as_ram.inc | 5 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 5 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram.inc | 5 |
4 files changed, 20 insertions, 0 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 6ff0287186..d8465f4b2f 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -221,6 +221,11 @@ clear_fixed_var_mtrr_out: */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index 03e0c2671c..9b7cad0cf9 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -97,6 +97,11 @@ clear_mtrrs: #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 6d88e7b8e5..acd0427c51 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -97,6 +97,11 @@ clear_mtrrs: #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 526d24520d..c270e44330 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -104,6 +104,11 @@ clear_mtrrs: #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr |