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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-01 07:27:51 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-01 07:27:51 +0000 |
| commit | 66d1687b927a94991233d1ee87dc916fb6ae033f (patch) | |
| tree | 0042583218104878a3f2d09bfe43f3ee9f33b541 /src/cpu/intel | |
| parent | 52000e1688e3b3f0c4cd62c4faa102737055d5e1 (diff) | |
| download | coreboot-66d1687b927a94991233d1ee87dc916fb6ae033f.tar.xz | |
CAR simplifications, typos, readability improvements (trivial).
- Use some more #defines instead of hard-coding values.
- Merge multiple movl/orl or movl/andl lines into one where possible.
- Add some TODOs in places which seem to have either an incorrect
code or incorrect comment.
- Fix typos: s/for/from/, s/BSC/BSP/, s/size/carsize/.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram.inc | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index ea455bfce3..98d227db2f 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -110,7 +110,7 @@ NotHtProcessor: /* Set the default memory type and enable fixed and variable MTRRs. */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */ + movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax wrmsr /* Clear all MTRRs. */ @@ -169,7 +169,7 @@ clear_fixed_var_mtrr_out: .endm /* - * size is the cache size in bytes we want to use for CAR. + * carsize is the cache size in bytes we want to use for CAR. * windowoffset is the 32k-aligned window into CAR size. */ .macro simplemask carsize, windowoffset @@ -221,8 +221,7 @@ clear_fixed_var_mtrr_out: */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $REAL_XIP_ROM_BASE, %eax - orl $MTRR_TYPE_WRBACK, %eax + movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx @@ -233,7 +232,7 @@ clear_fixed_var_mtrr_out: /* Enable cache. */ movl %cr0, %eax - andl $0x9fffffff, %eax + andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -303,7 +302,7 @@ lout: pushl %eax /* BIST */ call main - /* We don't need CAR for now on. */ + /* We don't need CAR from now on. */ /* Disable cache. */ movl %cr0, %eax @@ -332,7 +331,7 @@ lout: /* Enable cache. */ movl %cr0, %eax - andl $0x9fffffff, %eax + andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 /* Clear boot_complete flag. */ |