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| author | Myles Watson <mylesgw@gmail.com> | 2010-10-01 15:16:20 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2010-10-01 15:16:20 +0000 |
| commit | c7e982bbefc70acebd79c051e64fb25df6e8b668 (patch) | |
| tree | 81c116a6dd2ea7a5f9b407a019d94e39dc0b4252 /src/cpu/intel | |
| parent | e82618d03719e1c3f012b6ac227aa4b34ae4950b (diff) | |
| download | coreboot-c7e982bbefc70acebd79c051e64fb25df6e8b668.tar.xz | |
Fix some breakage from 5890.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram.inc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 98d227db2f..8491d86db2 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -221,7 +221,8 @@ clear_fixed_var_mtrr_out: */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx |