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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 11:46:50 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-08 22:16:31 +0000 |
| commit | 284a54775bf17f5192b164a4b9d09a06fcd747cd (patch) | |
| tree | cf6b6207ee908da0529b660f10f35e0b9afcc4cd /src/cpu/intel | |
| parent | e816829e7a422d588fc9ff6a11507c15e6be696c (diff) | |
| download | coreboot-284a54775bf17f5192b164a4b9d09a06fcd747cd.tar.xz | |
nb/intel/haswell: Drop unnecessary variable
The "normalized" boot mode is only used in a single place, so there's no
need to use a variable. Also, reword the associated comment, which seems
to be unnecessarily vague: the hardcoded assumptions are inside the MRC.
Change-Id: I260d10f231f5de765d2675416d7047717d391d8f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 381d7bfcb5..7886de07ed 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -15,7 +15,6 @@ void romstage_common(const struct romstage_params *params) { - int boot_mode; int wake_from_s3; enable_lapic(); @@ -37,16 +36,14 @@ void romstage_common(const struct romstage_params *params) #endif } - /* There are hard coded assumptions of 2 meaning s3 wake. Normalize - * the users of the 2 literal here based off wake_from_s3. */ - boot_mode = wake_from_s3 ? 2 : 0; - /* Prepare USB controller early in S3 resume */ if (wake_from_s3) enable_usb_bar(); post_code(0x3a); - params->pei_data->boot_mode = boot_mode; + + /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ + params->pei_data->boot_mode = wake_from_s3 ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); |