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| author | Marc Jones <marc.jones@se-eng.com> | 2012-10-25 09:37:19 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-12 03:27:45 +0100 |
| commit | 5986edadff53075f4bb5fe419514962c96f9faf6 (patch) | |
| tree | ab76a8d87ed2c6b3d5c769a7e5a4faa0ac350086 /src/cpu/intel | |
| parent | bb9dff55560e2f1834ec9bb41d4929ed3c749818 (diff) | |
| download | coreboot-5986edadff53075f4bb5fe419514962c96f9faf6.tar.xz | |
Revert "Remove code that enables/disables VMX in coreboot on chromebooks."
The MSR for VMX can start with a random value and needs to be
cleared by coreboot. I am reverting this change, as
it handles almost everything and doing a follow-on change to fix
the improper clearing of the MSR.
Change-Id: Ibad7a27b03f199241c52c1ebdd2b6d4e81a18a4e
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1793
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/model_206ax/Kconfig | 4 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/finalize.c | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/model_206ax_init.c | 38 |
3 files changed, 43 insertions, 0 deletions
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 5c543b88ba..5b3f893943 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -28,6 +28,10 @@ config SMM_TSEG_SIZE hex default 0x800000 +config ENABLE_VMX + bool "Enable VMX for virtualization" + default n + config MICROCODE_INCLUDE_PATH string default "src/cpu/intel/model_206ax" diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 4ed5d1e5f8..ca7048d50b 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -43,6 +43,7 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_model_206ax_finalize_smm(void) { + msr_set_bit(IA32_FEATURE_CONTROL, 0); msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 9654af14c5..47c7707548 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -116,6 +116,41 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; +static void enable_vmx(void) +{ + struct cpuid_result regs; + msr_t msr; + int enable = CONFIG_ENABLE_VMX; + + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + printk(BIOS_ERR, "VMX is locked, so enable_vmx will do nothing\n"); + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + regs = cpuid(1); + printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + if (regs.ecx & CPUID_VMX) { + if (enable) + msr.lo |= (1 << 2); + else + msr.lo &= ~(1 << 2); + + if (regs.ecx & CPUID_SMX) { + if (enable) + msr.lo |= (1 << 1); + else + msr.lo &= ~(1 << 1); + } + } + + wrmsr(IA32_FEATURE_CONTROL, msr); +} + /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -526,6 +561,9 @@ static void model_206ax_init(device_t cpu) enable_lapic_tpr(); setup_lapic(); + /* Enable virtualization if enabled in CMOS */ + enable_vmx(); + /* Configure C States */ configure_c_states(); |