diff options
| author | Keith Hui <buurin@gmail.com> | 2017-09-01 17:10:33 -0400 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-12 07:52:24 +0000 |
| commit | 47b283605a999565d54876c25026215daf2debbd (patch) | |
| tree | ee603634c61667a5695df26b4197c5049725e3ab /src/cpu/intel | |
| parent | b8e325a7140020caf7f0f3bc82a1606c9fa4d15e (diff) | |
| download | coreboot-47b283605a999565d54876c25026215daf2debbd.tar.xz | |
cpu/intel/car/cache_as_ram.inc: Remove broken HT code
Remove Hyperthreading related code that was missing setup of SIPI
vector and did not work.
Change-Id: I27e329a7b667ce4405fe07a637edbc6b5be22f2d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21375
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram.inc | 75 |
1 files changed, 0 insertions, 75 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index ac17571783..baa10c0ab0 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -29,81 +29,6 @@ movl %eax, %ebp CacheAsRam: - /* Check whether the processor has HT capability. */ - movl $01, %eax - cpuid - btl $28, %edx - jnc NotHtProcessor - bswapl %ebx - cmpb $01, %bh - jbe NotHtProcessor - - /* - * It is a HT processor. Send SIPI to the other logical processor - * within this processor so that the CAR related common system - * registers are programmed accordingly. - */ - - /* - * Use some register that is common to both logical processors - * as semaphore. Refer Appendix B, Vol.3. - */ - xorl %eax, %eax - xorl %edx, %edx - movl $MTRR_FIX_64K_00000, %ecx - wrmsr - - /* - * Figure out the logical AP's APIC ID; the following logic will - * work only for processors with 2 threads. - * Refer to Vol 3. Table 7-1 for details about this logic. - */ - movl $0xFEE00020, %esi - movl (%esi), %ebx - andl $0xFF000000, %ebx - bswapl %ebx - btl $0, %ebx - jnc LogicalAP0 - andb $0xFE, %bl - jmp Send_SIPI -LogicalAP0: - orb $0x01, %bl -Send_SIPI: - bswapl %ebx /* EBX - logical AP's APIC ID. */ - - /* - * Fill up the IPI command registers in the Local APIC mapped to - * default address and issue SIPI to the other logical processor - * within this processor die. - */ -Retry_SIPI: - movl %ebx, %eax - movl $0xFEE00310, %esi - movl %eax, (%esi) - - /* SIPI vector - F900:0000 */ - movl $0x000006F9, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - movl $0x30, %ecx -SIPI_Delay: - pause - decl %ecx - jnz SIPI_Delay - - movl (%esi), %eax - andl $0x00001000, %eax - jnz Retry_SIPI - - /* Wait for the Logical AP to complete initialization. */ -LogicalAP_SIPINotdone: - movl $MTRR_FIX_64K_00000, %ecx - rdmsr - orl %eax, %eax - jz LogicalAP_SIPINotdone - -NotHtProcessor: /* Set the default memory type and enable fixed and variable MTRRs. */ movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx |