diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-09-28 09:06:43 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-11 21:05:07 +0000 |
| commit | 603963e1ba4147ef31a72b94304708ab416e3b6a (patch) | |
| tree | a6ea32124fe96635dd637333859e7daa6a6e5b73 /src/cpu/intel | |
| parent | de5d04011cb2f3de4e93381d58a4d01d5682a3f9 (diff) | |
| download | coreboot-603963e1ba4147ef31a72b94304708ab416e3b6a.tar.xz | |
src: Replace MSR addresses with macros
Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/microcode/microcode.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 60342359c2..ae34347e26 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -102,7 +102,7 @@ void intel_microcode_load_unlocked(const void *microcode_patch) msr.lo = (unsigned long)m + sizeof(struct microcode); msr.hi = 0; - wrmsr(0x79, msr); + wrmsr(IA32_BIOS_UPDT_TRIG, msr); #if !defined(__ROMCC__) printk(BIOS_DEBUG, "microcode: updated to revision " @@ -158,12 +158,12 @@ const void *intel_microcode_find(void) return NULL; #endif - /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ + /* CPUID sets MSR 0x8B if a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0; - wrmsr(0x8B, msr); + wrmsr(IA32_BIOS_SIGN_ID, msr); eax = cpuid_eax(1); - msr = rdmsr(0x8B); + msr = rdmsr(IA32_BIOS_SIGN_ID); rev = msr.hi; x86_model = (eax >> 4) & 0x0f; x86_family = (eax >> 8) & 0x0f; @@ -171,7 +171,7 @@ const void *intel_microcode_find(void) pf = 0; if ((x86_model >= 5) || (x86_family > 6)) { - msr = rdmsr(0x17); + msr = rdmsr(IA32_PLATFORM_ID); pf = 1 << ((msr.hi >> 18) & 7); } #if !defined(__ROMCC__) |