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| author | Philipp Deppenwiese <zaolin@das-labor.org> | 2017-10-18 17:13:07 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2018-01-18 01:35:31 +0000 |
| commit | 64e2d19082636de9e82674ccfca574269bb34712 (patch) | |
| tree | dfe44c9b1cebbb611b99474c1ee096e23f930796 /src/cpu/intel | |
| parent | 4fef7818ecd002e5971ea6287e402fd9276b7266 (diff) | |
| download | coreboot-64e2d19082636de9e82674ccfca574269bb34712.tar.xz | |
security/tpm: Move tpm TSS and TSPI layer to security section
* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 136f098e71..ffbfbdfd83 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -42,7 +42,7 @@ #include "northbridge/intel/haswell/raminit.h" #include "southbridge/intel/lynxpoint/pch.h" #include "southbridge/intel/lynxpoint/me.h" -#include <tpm.h> +#include <security/tpm/tpm.h> static inline void reset_system(void) { |