haswell: Add initial support for Haswell platforms

The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore, the southbridge support is included as well. The basis for this code is the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires more attention, but this is a good starting point. This code partially gets up through the romstage just before training memory on a Haswell reference board. Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2616 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
author: Aaron Durbin <adurbin@chromium.org> 2012-10-30 09:03:43 -0500
committer: Ronald G. Minnich <rminnich@gmail.com> 2013-03-14 01:44:40 +0100
commit: 76c3700f02f79b49fec30d6ef18d336f122cbf50 (patch)
tree: cb1c750ef3946e2ae462e1847ec89946579274b2 /src/cpu/intel
parent: cc86e63e835ab0bceb62215460a13266a791cdd3 (diff)
download: coreboot-76c3700f02f79b49fec30d6ef18d336f122cbf50.tar.xz
18 files changed, 6060 insertions, 0 deletions
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index c3cf4c9fa3..45071d0c7e 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -16,6 +16,7 @@ source src/cpu/intel/model_f2x/Kconfig
 source src/cpu/intel/model_f3x/Kconfig
 source src/cpu/intel/model_f4x/Kconfig
 source src/cpu/intel/ep80579/Kconfig
+source src/cpu/intel/haswell/Kconfig
 # Sockets/Slots
 source src/cpu/intel/slot_2/Kconfig
 source src/cpu/intel/slot_1/Kconfig
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 782c15ab3e..a1733297c1 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -17,6 +17,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
 subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
new file mode 100644
index 0000000000..5b24a8bce4
--- /dev/null
+++ b/src/cpu/intel/haswell/Kconfig
@@ -0,0 +1,33 @@
+
+config CPU_INTEL_HASWELL
+	bool
+
+if CPU_INTEL_HASWELL
+
+config CPU_SPECIFIC_OPTIONS
+	def_bool y
+	select SMP
+	select SSE2
+	select UDELAY_LAPIC
+	select SMM_TSEG
+	select CPU_MICROCODE_IN_CBFS
+	#select AP_IN_SIPI_WAIT
+	select TSC_SYNC_MFENCE
+
+config BOOTBLOCK_CPU_INIT
+	string
+	default "cpu/intel/haswell/bootblock.c"
+
+config SERIAL_CPU_INIT
+	bool
+	default n
+
+config SMM_TSEG_SIZE
+	hex
+	default 0x800000
+
+config MICROCODE_INCLUDE_PATH
+	string
+	default "src/cpu/intel/haswell"
+
+endif
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
new file mode 100644
index 0000000000..467c948430
--- /dev/null
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -0,0 +1,10 @@
+ramstage-y += haswell_init.c
+subdirs-y += ../../x86/name
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+
+cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
new file mode 100644
index 0000000000..c0df9f6f37
--- /dev/null
+++ b/src/cpu/intel/haswell/acpi.c
@@ -0,0 +1,364 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include "haswell.h"
+#include "chip.h"
+
+static int get_cores_per_package(void)
+{
+	struct cpuinfo_x86 c;
+	struct cpuid_result result;
+	int cores = 1;
+
+	get_fms(&c, cpuid_eax(1));
+	if (c.x86 != 6)
+		return 1;
+
+	result = cpuid_ext(0xb, 1);
+	cores = result.ebx & 0xff;
+
+	return cores;
+}
+
+static int generate_cstate_entries(acpi_cstate_t *cstates,
+				   int c1, int c2, int c3)
+{
+	int length, cstate_count = 0;
+
+	/* Count number of active C-states */
+	if (c1 > 0)
+		++cstate_count;
+	if (c2 > 0)
+		++cstate_count;
+	if (c3 > 0)
+		++cstate_count;
+	if (!cstate_count)
+		return 0;
+
+	length = acpigen_write_package(cstate_count + 1);
+	length += acpigen_write_byte(cstate_count);
+
+	/* Add an entry if the level is enabled */
+	if (c1 > 0) {
+		cstates[c1].ctype = 1;
+		length += acpigen_write_CST_package_entry(&cstates[c1]);
+	}
+	if (c2 > 0) {
+		cstates[c2].ctype = 2;
+		length += acpigen_write_CST_package_entry(&cstates[c2]);
+	}
+	if (c3 > 0) {
+		cstates[c3].ctype = 3;
+		length += acpigen_write_CST_package_entry(&cstates[c3]);
+	}
+
+	acpigen_patch_len(length - 1);
+	return length;
+}
+
+static int generate_C_state_entries(void)
+{
+	struct cpu_info *info;
+	struct cpu_driver *cpu;
+	int len, lenif;
+	device_t lapic;
+	struct cpu_intel_haswell_config *conf = NULL;
+
+	/* Find the SpeedStep CPU in the device tree using magic APIC ID */
+	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (!lapic)
+		return 0;
+	conf = lapic->chip_info;
+	if (!conf)
+		return 0;
+
+	/* Find CPU map of supported C-states */
+	info = cpu_info();
+	if (!info)
+		return 0;
+	cpu = find_cpu_driver(info->cpu);
+	if (!cpu || !cpu->cstates)
+		return 0;
+
+	len = acpigen_emit_byte(0x14);		/* MethodOp */
+	len += acpigen_write_len_f();		/* PkgLength */
+	len += acpigen_emit_namestring("_CST");
+	len += acpigen_emit_byte(0x00);		/* No Arguments */
+
+	/* If running on AC power */
+	len += acpigen_emit_byte(0xa0);		/* IfOp */
+	lenif = acpigen_write_len_f();		/* PkgLength */
+	lenif += acpigen_emit_namestring("PWRS");
+	lenif += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
+					 conf->c2_acpower, conf->c3_acpower);
+	acpigen_patch_len(lenif - 1);
+	len += lenif;
+
+	/* Else on battery power */
+	len += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	len += generate_cstate_entries(cpu->cstates, conf->c1_battery,
+					conf->c2_battery, conf->c3_battery);
+	acpigen_patch_len(len - 1);
+	return len;
+}
+
+static acpi_tstate_t tss_table_fine[] = {
+	{ 100, 1000, 0, 0x00, 0 },
+	{ 94, 940, 0, 0x1f, 0 },
+	{ 88, 880, 0, 0x1e, 0 },
+	{ 82, 820, 0, 0x1d, 0 },
+	{ 75, 760, 0, 0x1c, 0 },
+	{ 69, 700, 0, 0x1b, 0 },
+	{ 63, 640, 0, 0x1a, 0 },
+	{ 57, 580, 0, 0x19, 0 },
+	{ 50, 520, 0, 0x18, 0 },
+	{ 44, 460, 0, 0x17, 0 },
+	{ 38, 400, 0, 0x16, 0 },
+	{ 32, 340, 0, 0x15, 0 },
+	{ 25, 280, 0, 0x14, 0 },
+	{ 19, 220, 0, 0x13, 0 },
+	{ 13, 160, 0, 0x12, 0 },
+};
+
+static acpi_tstate_t tss_table_coarse[] = {
+	{ 100, 1000, 0, 0x00, 0 },
+	{ 88, 875, 0, 0x1f, 0 },
+	{ 75, 750, 0, 0x1e, 0 },
+	{ 63, 625, 0, 0x1d, 0 },
+	{ 50, 500, 0, 0x1c, 0 },
+	{ 38, 375, 0, 0x1b, 0 },
+	{ 25, 250, 0, 0x1a, 0 },
+	{ 13, 125, 0, 0x19, 0 },
+};
+
+static int generate_T_state_entries(int core, int cores_per_package)
+{
+	int len;
+
+	/* Indicate SW_ALL coordination for T-states */
+	len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
+
+	/* Indicate FFixedHW so OS will use MSR */
+	len += acpigen_write_empty_PTC();
+
+	/* Set a T-state limit that can be modified in NVS */
+	len += acpigen_write_TPC("\\TLVL");
+
+	/*
+	 * CPUID.(EAX=6):EAX[5] indicates support
+	 * for extended throttle levels.
+	 */
+	if (cpuid_eax(6) & (1 << 5))
+		len += acpigen_write_TSS_package(
+			ARRAY_SIZE(tss_table_fine), tss_table_fine);
+	else
+		len += acpigen_write_TSS_package(
+			ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
+
+	return len;
+}
+
+static int calculate_power(int tdp, int p1_ratio, int ratio)
+{
+	u32 m;
+	u32 power;
+
+	/*
+	 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
+	 *
+	 * Power = (ratio / p1_ratio) * m * tdp
+	 */
+
+	m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
+	m = (m * m) / 1000;
+
+	power = ((ratio * 100000 / p1_ratio) / 100);
+	power *= (m / 100) * (tdp / 1000);
+	power /= 1000;
+
+	return (int)power;
+}
+
+static int generate_P_state_entries(int core, int cores_per_package)
+{
+	int len, len_pss;
+	int ratio_min, ratio_max, ratio_turbo, ratio_step;
+	int coord_type, power_max, power_unit, num_entries;
+	int ratio, power, clock, clock_max;
+	msr_t msr;
+
+	/* Determine P-state coordination type from MISC_PWR_MGMT[0] */
+	msr = rdmsr(MSR_MISC_PWR_MGMT);
+	if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
+		coord_type = SW_ANY;
+	else
+		coord_type = HW_ALL;
+
+	/* Get bus ratio limits and calculate clock speeds */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
+
+	/* Determine if this CPU has configurable TDP */
+	if (cpu_config_tdp_levels()) {
+		/* Set max ratio to nominal TDP ratio */
+		msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+		ratio_max = msr.lo & 0xff;
+	} else {
+		/* Max Non-Turbo Ratio */
+		ratio_max = (msr.lo >> 8) & 0xff;
+	}
+	clock_max = ratio_max * HASWELL_BCLK;
+
+	/* Calculate CPU TDP in mW */
+	msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
+	power_unit = 2 << ((msr.lo & 0xf) - 1);
+	msr = rdmsr(MSR_PKG_POWER_SKU);
+	power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
+
+	/* Write _PCT indicating use of FFixedHW */
+	len = acpigen_write_empty_PCT();
+
+	/* Write _PPC with no limit on supported P-state */
+	len += acpigen_write_PPC_NVS();
+
+	/* Write PSD indicating configured coordination type */
+	len += acpigen_write_PSD_package(core, cores_per_package, coord_type);
+
+	/* Add P-state entries in _PSS table */
+	len += acpigen_write_name("_PSS");
+
+	/* Determine ratio points */
+	ratio_step = PSS_RATIO_STEP;
+	num_entries = (ratio_max - ratio_min) / ratio_step;
+	while (num_entries > PSS_MAX_ENTRIES-1) {
+		ratio_step <<= 1;
+		num_entries >>= 1;
+	}
+
+	/* P[T] is Turbo state if enabled */
+	if (get_turbo_state() == TURBO_ENABLED) {
+		/* _PSS package count including Turbo */
+		len_pss = acpigen_write_package(num_entries + 2);
+
+		msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
+		ratio_turbo = msr.lo & 0xff;
+
+		/* Add entry for Turbo ratio */
+		len_pss += acpigen_write_PSS_package(
+			clock_max + 1,		/*MHz*/
+			power_max,		/*mW*/
+			PSS_LATENCY_TRANSITION,	/*lat1*/
+			PSS_LATENCY_BUSMASTER,	/*lat2*/
+			ratio_turbo << 8,	/*control*/
+			ratio_turbo << 8);	/*status*/
+	} else {
+		/* _PSS package count without Turbo */
+		len_pss = acpigen_write_package(num_entries + 1);
+	}
+
+	/* First regular entry is max non-turbo ratio */
+	len_pss += acpigen_write_PSS_package(
+		clock_max,		/*MHz*/
+		power_max,		/*mW*/
+		PSS_LATENCY_TRANSITION,	/*lat1*/
+		PSS_LATENCY_BUSMASTER,	/*lat2*/
+		ratio_max << 8,		/*control*/
+		ratio_max << 8);	/*status*/
+
+	/* Generate the remaining entries */
+	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
+	     ratio >= ratio_min; ratio -= ratio_step) {
+
+		/* Calculate power at this ratio */
+		power = calculate_power(power_max, ratio_max, ratio);
+		clock = ratio * HASWELL_BCLK;
+
+		len_pss += acpigen_write_PSS_package(
+			clock,			/*MHz*/
+			power,			/*mW*/
+			PSS_LATENCY_TRANSITION,	/*lat1*/
+			PSS_LATENCY_BUSMASTER,	/*lat2*/
+			ratio << 8,		/*control*/
+			ratio << 8);		/*status*/
+	}
+
+	/* Fix package length */
+	len_pss--;
+	acpigen_patch_len(len_pss);
+
+	return len + len_pss;
+}
+
+void generate_cpu_entries(void)
+{
+	int len_pr;
+	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
+	int totalcores = dev_count_cpu();
+	int cores_per_package = get_cores_per_package();
+	int numcpus = totalcores/cores_per_package;
+
+	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
+	       numcpus, cores_per_package);
+
+	for (cpuID=1; cpuID <=numcpus; cpuID++) {
+		for (coreID=1; coreID<=cores_per_package; coreID++) {
+			if (coreID>1) {
+				pcontrol_blk = 0;
+				plen = 0;
+			}
+
+			/* Generate processor \_PR.CPUx */
+			len_pr = acpigen_write_processor(
+				(cpuID-1)*cores_per_package+coreID-1,
+				pcontrol_blk, plen);
+
+			/* Generate P-state tables */
+			len_pr += generate_P_state_entries(
+				cpuID-1, cores_per_package);
+
+			/* Generate C-state tables */
+			len_pr += generate_C_state_entries();
+
+			/* Generate T-state tables */
+			len_pr += generate_T_state_entries(
+				cpuID-1, cores_per_package);
+
+			len_pr--;
+			acpigen_patch_len(len_pr);
+		}
+	}
+}
+
+struct chip_operations cpu_intel_haswell_ops = {
+	CHIP_NAME("Intel Haswell CPU")
+};
diff --git a/src/cpu/intel/haswell/acpi/cpu.asl b/src/cpu/intel/haswell/acpi/cpu.asl
new file mode 100644
index 0000000000..558a9d3663
--- /dev/null
+++ b/src/cpu/intel/haswell/acpi/cpu.asl
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* These devices are created at runtime */
+External (\_PR.CPU0, DeviceObj)
+External (\_PR.CPU1, DeviceObj)
+External (\_PR.CPU2, DeviceObj)
+External (\_PR.CPU3, DeviceObj)
+External (\_PR.CPU4, DeviceObj)
+External (\_PR.CPU5, DeviceObj)
+External (\_PR.CPU6, DeviceObj)
+External (\_PR.CPU7, DeviceObj)
+
+/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
+Method (PNOT)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (\_PR.CPU0, 0x81)  // _CST
+		Notify (\_PR.CPU1, 0x81)  // _CST
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (\_PR.CPU2, 0x81)  // _CST
+		Notify (\_PR.CPU3, 0x81)  // _CST
+	}
+	If (LGreaterEqual (\PCNT, 8)) {
+		Notify (\_PR.CPU4, 0x81)  // _CST
+		Notify (\_PR.CPU5, 0x81)  // _CST
+		Notify (\_PR.CPU6, 0x81)  // _CST
+		Notify (\_PR.CPU7, 0x81)  // _CST
+	}
+}
+
+/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
+Method (PPCN)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (\_PR.CPU0, 0x80)  // _PPC
+		Notify (\_PR.CPU1, 0x80)  // _PPC
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (\_PR.CPU2, 0x80)  // _PPC
+		Notify (\_PR.CPU3, 0x80)  // _PPC
+	}
+	If (LGreaterEqual (\PCNT, 8)) {
+		Notify (\_PR.CPU4, 0x80)  // _PPC
+		Notify (\_PR.CPU5, 0x80)  // _PPC
+		Notify (\_PR.CPU6, 0x80)  // _PPC
+		Notify (\_PR.CPU7, 0x80)  // _PPC
+	}
+}
+
+/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
+Method (TNOT)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (\_PR.CPU0, 0x82)  // _TPC
+		Notify (\_PR.CPU1, 0x82)  // _TPC
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (\_PR.CPU2, 0x82)  // _TPC
+		Notify (\_PR.CPU3, 0x82)  // _TPC
+	}
+	If (LGreaterEqual (\PCNT, 8)) {
+		Notify (\_PR.CPU4, 0x82)  // _TPC
+		Notify (\_PR.CPU5, 0x82)  // _TPC
+		Notify (\_PR.CPU6, 0x82)  // _TPC
+		Notify (\_PR.CPU7, 0x82)  // _TPC
+	}
+}
+
+/* Return a package containing enabled processor entries */
+Method (PPKG)
+{
+	If (LGreaterEqual (\PCNT, 8)) {
+		Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3,
+				   \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7})
+	} ElseIf (LGreaterEqual (\PCNT, 4)) {
+		Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3})
+	} ElseIf (LGreaterEqual (\PCNT, 2)) {
+		Return (Package() {\_PR.CPU0, \_PR.CPU1})
+	} Else {
+		Return (Package() {\_PR.CPU0})
+	}
+}
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c
new file mode 100644
index 0000000000..f9c3ba8d6f
--- /dev/null
+++ b/src/cpu/intel/haswell/bootblock.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#include <cpu/intel/microcode/microcode.c>
+#include "haswell.h"
+
+#if CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT
+/* Needed for RCBA access to set Soft Reset Data register */
+#include <southbridge/intel/lynxpoint/pch.h>
+#else
+#error "CPU must be paired with Intel LynxPoint southbridge"
+#endif
+
+static void set_var_mtrr(
+	unsigned reg, unsigned base, unsigned size, unsigned type)
+
+{
+	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+	/* FIXME: It only support 4G less range */
+	msr_t basem, maskm;
+	basem.lo = base | type;
+	basem.hi = 0;
+	wrmsr(MTRRphysBase_MSR(reg), basem);
+	maskm.lo = ~(size - 1) | MTRRphysMaskValid;
+	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
+	wrmsr(MTRRphysMask_MSR(reg), maskm);
+}
+
+static void enable_rom_caching(void)
+{
+	msr_t msr;
+
+	disable_cache();
+	/* Why only top 4MiB ? */
+	set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
+	enable_cache();
+
+	/* Enable Variable MTRRs */
+	msr.hi = 0x00000000;
+	msr.lo = 0x00000800;
+	wrmsr(MTRRdefType_MSR, msr);
+}
+
+static void set_flex_ratio_to_tdp_nominal(void)
+{
+	msr_t flex_ratio, msr;
+	u32 soft_reset;
+	u8 nominal_ratio;
+
+	/* Check for Flex Ratio support */
+	flex_ratio = rdmsr(MSR_FLEX_RATIO);
+	if (!(flex_ratio.lo & FLEX_RATIO_EN))
+		return;
+
+	/* Check for >0 configurable TDPs */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if (((msr.hi >> 1) & 3) == 0)
+		return;
+
+	/* Use nominal TDP ratio for flex ratio */
+	msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+	nominal_ratio = msr.lo & 0xff;
+
+	/* See if flex ratio is already set to nominal TDP ratio */
+	if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
+		return;
+
+	/* Set flex ratio to nominal TDP ratio */
+	flex_ratio.lo &= ~0xff00;
+	flex_ratio.lo |= nominal_ratio << 8;
+	flex_ratio.lo |= FLEX_RATIO_LOCK;
+	wrmsr(MSR_FLEX_RATIO, flex_ratio);
+
+	/* Set flex ratio in soft reset data register bits 11:6.
+	 * RCBA region is enabled in southbridge bootblock */
+	soft_reset = RCBA32(SOFT_RESET_DATA);
+	soft_reset &= ~(0x3f << 6);
+	soft_reset |= (nominal_ratio & 0x3f) << 6;
+	RCBA32(SOFT_RESET_DATA) = soft_reset;
+
+	/* Set soft reset control to use register value */
+	RCBA32_OR(SOFT_RESET_CTRL, 1);
+
+	/* Issue warm reset, will be "CPU only" due to soft reset data */
+	outb(0x0, 0xcf9);
+	outb(0x6, 0xcf9);
+	while (1) {
+		asm("hlt");
+	}
+}
+
+static void bootblock_cpu_init(void)
+{
+	/* Set flex ratio and reset if needed */
+	set_flex_ratio_to_tdp_nominal();
+	enable_rom_caching();
+	intel_update_microcode_from_cbfs();
+}
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
new file mode 100644
index 0000000000..f5ee82e2d2
--- /dev/null
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -0,0 +1,349 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cpu/x86/stack.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+#include <cbmem.h>
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+/* Cache 4GB - MRC_SIZE_KB for MRC */
+#define CACHE_MRC_BYTES   ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
+#define CACHE_MRC_BASE    (0xFFFFFFFF - CACHE_MRC_BYTES)
+#define CACHE_MRC_MASK    (~CACHE_MRC_BYTES)
+
+#define CPU_MAXPHYSADDR CONFIG_CPU_ADDR_BITS
+#define CPU_PHYSMASK_HI  (1 << (CPU_MAXPHYSADDR - 32) - 1)
+
+#define NoEvictMod_MSR 0x2e0
+
+	/* Save the BIST result. */
+	movl	%eax, %ebp
+
+cache_as_ram:
+	post_code(0x20)
+
+	/* Send INIT IPI to all excluding ourself. */
+	movl	$0x000C4500, %eax
+	movl	$0xFEE00300, %esi
+	movl	%eax, (%esi)
+
+	/* All CPUs need to be in Wait for SIPI state */
+wait_for_sipi:
+	movl	(%esi), %eax
+	bt	$12, %eax
+	jc	wait_for_sipi
+
+	post_code(0x21)
+	/* Zero out all fixed range and variable range MTRRs. */
+	movl	$mtrr_table, %esi
+	movl	$((mtrr_table_end - mtrr_table) / 2), %edi
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+clear_mtrrs:
+	movw	(%esi), %bx
+	movzx	%bx, %ecx
+	wrmsr
+	add	$2, %esi
+	dec	%edi
+	jnz	clear_mtrrs
+
+	post_code(0x22)
+	/* Configure the default memory type to uncacheable. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~0x00000cff), %eax
+	wrmsr
+
+	post_code(0x23)
+	/* Set Cache-as-RAM base address. */
+	movl	$(MTRRphysBase_MSR(0)), %ecx
+	movl	$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	post_code(0x24)
+	/* Set Cache-as-RAM mask. */
+	movl	$(MTRRphysMask_MSR(0)), %ecx
+	movl	$(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+	movl	$CPU_PHYSMASK_HI, %edx
+	wrmsr
+
+	post_code(0x25)
+
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$MTRRdefTypeEn, %eax
+	wrmsr
+
+	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+        movl	%cr0, %eax
+	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+	invd
+	movl	%eax, %cr0
+
+	/* enable the 'no eviction' mode */
+	movl    $NoEvictMod_MSR, %ecx
+	rdmsr
+	orl     $1, %eax
+	andl    $~2, %eax
+	wrmsr
+
+       /* Clear the cache memory region. This will also fill up the cache */
+	movl	$CACHE_AS_RAM_BASE, %esi
+	movl	%esi, %edi
+	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
+	// movl	$0x23322332, %eax
+	xorl	%eax, %eax
+	rep	stosl
+
+	/* enable the 'no eviction run' state */
+	movl    $NoEvictMod_MSR, %ecx
+	rdmsr
+	orl     $3, %eax
+	wrmsr
+
+	post_code(0x26)
+	/* Enable Cache-as-RAM mode by disabling cache. */
+	movl	%cr0, %eax
+	orl	$CR0_CacheDisable, %eax
+	movl	%eax, %cr0
+
+	/* Enable cache for our code in Flash because we do XIP here */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	xorl	%edx, %edx
+	/*
+	 * IMPORTANT: The following calculation _must_ be done at runtime. See
+	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 */
+	movl    $copy_and_run, %eax
+	andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
+	wrmsr
+
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$CPU_PHYSMASK_HI, %edx
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+	wrmsr
+
+	post_code(0x27)
+#if CONFIG_CACHE_MRC_BIN
+	/* Enable caching for ram init code to run faster */
+	movl	$MTRRphysBase_MSR(2), %ecx
+	movl	$(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(2), %ecx
+	movl	$(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
+	movl	$CPU_PHYSMASK_HI, %edx
+	wrmsr
+#endif
+
+	post_code(0x28)
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+	movl	%eax, %cr0
+
+	/* Set up the stack pointer below MRC variable space. */
+	movl	$(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \
+		  CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4), %eax
+	movl	%eax, %esp
+
+	/* Restore the BIST result. */
+	movl	%ebp, %eax
+	movl	%esp, %ebp
+	pushl	%eax
+
+before_romstage:
+	post_code(0x29)
+	/* Call romstage.c main function. */
+	call	main
+
+	post_code(0x2f)
+
+	/* Copy global variable space (for USBDEBUG) to memory */
+#if CONFIG_USBDEBUG
+	cld
+	movl	$(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi
+	movl	$(CONFIG_RAMTOP - 24), %edi
+	movl	$24, %ecx
+	rep	movsb
+#endif
+
+	post_code(0x30)
+
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$CR0_CacheDisable, %eax
+	movl	%eax, %cr0
+
+	post_code(0x31)
+
+	/* Disable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~MTRRdefTypeEn), %eax
+	wrmsr
+
+	post_code(0x31)
+
+	/* Disable the no eviction run state */
+	movl    $NoEvictMod_MSR, %ecx
+	rdmsr
+	andl    $~2, %eax
+	wrmsr
+
+	invd
+
+	/* Disable the no eviction mode */
+	rdmsr
+	andl    $~1, %eax
+	wrmsr
+
+#if CONFIG_CACHE_MRC_BIN
+	/* Clear MTRR that was used to cache MRC */
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+	movl	$MTRRphysBase_MSR(2), %ecx
+	wrmsr
+	movl	$MTRRphysMask_MSR(2), %ecx
+	wrmsr
+#endif
+
+	post_code(0x33)
+
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
+	movl	%eax, %cr0
+
+	post_code(0x36)
+
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$CR0_CacheDisable, %eax
+	movl	%eax, %cr0
+
+	post_code(0x38)
+
+	/* Enable Write Back and Speculative Reads for the first MB
+	 * and coreboot_ram.
+	 */
+	movl	$MTRRphysBase_MSR(0), %ecx
+	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(0), %ecx
+	movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+	movl	$CPU_PHYSMASK_HI, %edx	// 36bit address space
+	wrmsr
+
+	/* Enable Caching and speculative Reads for the
+	 * complete ROM now that we actually have RAM.
+	 */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	movl	$(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax
+	movl	$CPU_PHYSMASK_HI, %edx
+	wrmsr
+
+	post_code(0x39)
+
+	/* And enable cache again after setting MTRRs. */
+	movl	%cr0, %eax
+	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
+	movl	%eax, %cr0
+
+	post_code(0x3a)
+
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$MTRRdefTypeEn, %eax
+	wrmsr
+
+	post_code(0x3b)
+
+	/* Invalidate the cache again. */
+	invd
+
+	post_code(0x3c)
+
+#if CONFIG_HAVE_ACPI_RESUME
+	movl	CBMEM_BOOT_MODE, %eax
+	cmpl	$0x2, %eax // Resume?
+	jne	__acpi_resume_backup_done
+
+	/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+	 * through stage 2. We could keep stuff like stack and heap in high
+	 * tables memory completely, but that's a wonderful clean up task for
+	 * another day.
+	 */
+	cld
+	movl	$CONFIG_RAMBASE, %esi
+	movl	CBMEM_RESUME_BACKUP, %edi
+	movl	$HIGH_MEMORY_SAVE / 4, %ecx
+	rep	movsl
+
+__acpi_resume_backup_done:
+#endif
+
+	post_code(0x3d)
+
+	/* Clear boot_complete flag. */
+	xorl	%ebp, %ebp
+__main:
+	post_code(POST_PREPARE_RAMSTAGE)
+	cld			/* Clear direction flag. */
+
+	movl	%ebp, %esi
+
+	movl	$ROMSTAGE_STACK, %esp
+	movl	%esp, %ebp
+	pushl	%esi
+	call	copy_and_run
+
+.Lhlt:
+	post_code(POST_DEAD_CODE)
+	hlt
+	jmp	.Lhlt
+
+mtrr_table:
+	/* Fixed MTRRs */
+	.word 0x250, 0x258, 0x259
+	.word 0x268, 0x269, 0x26A
+	.word 0x26B, 0x26C, 0x26D
+	.word 0x26E, 0x26F
+	/* Variable MTRRs */
+	.word 0x200, 0x201, 0x202, 0x203
+	.word 0x204, 0x205, 0x206, 0x207
+	.word 0x208, 0x209, 0x20A, 0x20B
+	.word 0x20C, 0x20D, 0x20E, 0x20F
+	.word 0x210, 0x211, 0x212, 0x213
+mtrr_table_end:
+
diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h
new file mode 100644
index 0000000000..52020437f9
--- /dev/null
+++ b/src/cpu/intel/haswell/chip.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations cpu_intel_haswell_ops;
+
+/* Magic value used to locate this chip in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
+struct cpu_intel_haswell_config {
+	u8 disable_acpi;	/* Do not generate CPU ACPI tables */
+
+	u8 pstate_coord_type;	/* Processor Coordination Type */
+
+	int c1_battery;		/* ACPI C1 on Battery Power */
+	int c2_battery;		/* ACPI C2 on Battery Power */
+	int c3_battery;		/* ACPI C3 on Battery Power */
+
+	int c1_acpower;		/* ACPI C1 on AC Power */
+	int c2_acpower;		/* ACPI C2 on AC Power */
+	int c3_acpower;		/* ACPI C3 on AC Power */
+
+	int tcc_offset;		/* TCC Activation Offset */
+};
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c
new file mode 100644
index 0000000000..1731322d83
--- /dev/null
+++ b/src/cpu/intel/haswell/finalize.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include "haswell.h"
+
+#if 0
+static void msr_set_bit(unsigned reg, unsigned bit)
+{
+	msr_t msr = rdmsr(reg);
+
+	if (bit < 32) {
+		if (msr.lo & (1 << bit))
+			return;
+		msr.lo |= 1 << bit;
+	} else {
+		if (msr.hi & (1 << (bit - 32)))
+			return;
+		msr.hi |= 1 << (bit - 32);
+	}
+
+	wrmsr(reg, msr);
+}
+#endif
+
+void intel_cpu_haswell_finalize_smm(void)
+{
+#if 0
+	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
+
+	/* Lock AES-NI only if supported */
+	if (cpuid_ecx(1) & (1 << 25))
+		msr_set_bit(MSR_FEATURE_CONFIG, 0);
+
+#ifdef LOCK_POWER_CONTROL_REGISTERS
+	/*
+	 * Lock the power control registers.
+	 *
+	 * These registers can be left unlocked if modifying power
+	 * limits from the OS is desirable. Modifying power limits
+	 * from the OS can be especially useful for experimentation
+	 * during  early phases of system bringup while the thermal
+	 * power envelope is being proven.
+	 */
+
+	msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31);
+	msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31);
+	msr_set_bit(MSR_PKG_POWER_LIMIT, 63);
+	msr_set_bit(MSR_PP0_POWER_LIMIT, 31);
+	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
+#endif
+
+	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+	msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
+#endif
+}
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
new file mode 100644
index 0000000000..f5c580ec7e
--- /dev/null
+++ b/src/cpu/intel/haswell/haswell.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CPU_INTEL_HASWELL_H
+#define _CPU_INTEL_HASWELL_H
+
+/* Haswell bus clock is fixed at 100MHz */
+#define HASWELL_BCLK		100
+
+#define IA32_FEATURE_CONTROL		0x3a
+#define  CPUID_VMX			(1 << 5)
+#define  CPUID_SMX			(1 << 6)
+#define MSR_FEATURE_CONFIG		0x13c
+#define MSR_FLEX_RATIO			0x194
+#define  FLEX_RATIO_LOCK		(1 << 20)
+#define  FLEX_RATIO_EN			(1 << 16)
+#define IA32_PLATFORM_DCA_CAP		0x1f8
+#define IA32_MISC_ENABLE		0x1a0
+#define MSR_TEMPERATURE_TARGET		0x1a2
+#define IA32_PERF_CTL 			0x199
+#define IA32_THERM_INTERRUPT		0x19b
+#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
+#define  ENERGY_POLICY_PERFORMANCE	0
+#define  ENERGY_POLICY_NORMAL		6
+#define  ENERGY_POLICY_POWERSAVE	15
+#define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
+#define MSR_LT_LOCK_MEMORY		0x2e7
+#define IA32_MC0_STATUS 		0x401
+
+#define MSR_PIC_MSG_CONTROL		0x2e
+#define MSR_PLATFORM_INFO		0xce
+#define  PLATFORM_INFO_SET_TDP		(1 << 29)
+#define MSR_PMG_CST_CONFIG_CONTROL	0xe2
+#define MSR_PMG_IO_CAPTURE_BASE		0xe4
+
+#define MSR_MISC_PWR_MGMT		0x1aa
+#define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
+#define MSR_TURBO_RATIO_LIMIT		0x1ad
+#define MSR_POWER_CTL			0x1fc
+
+#define MSR_PKGC3_IRTL			0x60a
+#define MSR_PKGC6_IRTL			0x60b
+#define MSR_PKGC7_IRTL			0x60c
+#define  IRTL_VALID			(1 << 15)
+#define  IRTL_1_NS			(0 << 10)
+#define  IRTL_32_NS			(1 << 10)
+#define  IRTL_1024_NS			(2 << 10)
+#define  IRTL_32768_NS			(3 << 10)
+#define  IRTL_1048576_NS		(4 << 10)
+#define  IRTL_33554432_NS		(5 << 10)
+#define  IRTL_RESPONSE_MASK		(0x3ff)
+
+/* long duration in low dword, short duration in high dword */
+#define MSR_PKG_POWER_LIMIT		0x610
+#define  PKG_POWER_LIMIT_MASK		0x7fff
+#define  PKG_POWER_LIMIT_EN		(1 << 15)
+#define  PKG_POWER_LIMIT_CLAMP		(1 << 16)
+#define  PKG_POWER_LIMIT_TIME_SHIFT	17
+#define  PKG_POWER_LIMIT_TIME_MASK	0x7f
+
+#define MSR_PP0_CURRENT_CONFIG		0x601
+#define MSR_VR_CURRENT_CONFIG		0x601
+#define  PP0_CURRENT_LIMIT		(112 << 3) /* 112 A */
+#define MSR_PP1_CURRENT_CONFIG		0x602
+#define  PP1_CURRENT_LIMIT_SNB		(35 << 3) /* 35 A */
+#define  PP1_CURRENT_LIMIT_IVB		(50 << 3) /* 50 A */
+#define MSR_PKG_POWER_SKU_UNIT		0x606
+#define MSR_PKG_POWER_SKU		0x614
+#define MSR_PP0_POWER_LIMIT		0x638
+#define MSR_PP1_POWER_LIMIT		0x640
+
+#define MSR_CONFIG_TDP_NOMINAL		0x648
+#define MSR_CONFIG_TDP_LEVEL1		0x649
+#define MSR_CONFIG_TDP_LEVEL2		0x64a
+#define MSR_CONFIG_TDP_CONTROL		0x64b
+#define MSR_TURBO_ACTIVATION_RATIO	0x64c
+
+/* P-state configuration */
+#define PSS_MAX_ENTRIES			8
+#define PSS_RATIO_STEP			2
+#define PSS_LATENCY_TRANSITION		10
+#define PSS_LATENCY_BUSMASTER		10
+
+#ifndef __ROMCC__
+#ifdef __SMM__
+/* Lock MSRs */
+void intel_cpu_haswell_finalize_smm(void);
+#else
+/* Configure power limits for turbo mode */
+void set_power_limits(u8 power_limit_1_time);
+int cpu_config_tdp_levels(void);
+#endif
+#endif
+
+#endif
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
new file mode 100644
index 0000000000..01d151ee06
--- /dev/null
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -0,0 +1,572 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/name.h>
+#include <pc80/mc146818rtc.h>
+#include <usbdebug.h>
+#include "haswell.h"
+#include "chip.h"
+
+/*
+ * List of suported C-states in this processor
+ *
+ * Latencies are typical worst-case package exit time in uS
+ * taken from the SandyBridge BIOS specification.
+ */
+#if 0
+static acpi_cstate_t cstate_map[] = {
+	{	/* 0: C0 */
+	},{	/* 1: C1 */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x00,	/* MWAIT State 0 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 2: C1E */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x01,	/* MWAIT State 0 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 3: C3 */
+		.latency = 63,
+		.power = 500,
+		.resource = {
+			.addrl = 0x10,	/* MWAIT State 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 4: C6 */
+		.latency = 87,
+		.power = 350,
+		.resource = {
+			.addrl = 0x20,	/* MWAIT State 2 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 5: C7 */
+		.latency = 90,
+		.power = 200,
+		.resource = {
+			.addrl = 0x30,	/* MWAIT State 3 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 6: C7S */
+		.latency = 90,
+		.power = 200,
+		.resource = {
+			.addrl = 0x31,	/* MWAIT State 3 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{ 0 }
+};
+#endif
+
+/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
+static const u8 power_limit_time_sec_to_msr[] = {
+	[0]   = 0x00,
+	[1]   = 0x0a,
+	[2]   = 0x0b,
+	[3]   = 0x4b,
+	[4]   = 0x0c,
+	[5]   = 0x2c,
+	[6]   = 0x4c,
+	[7]   = 0x6c,
+	[8]   = 0x0d,
+	[10]  = 0x2d,
+	[12]  = 0x4d,
+	[14]  = 0x6d,
+	[16]  = 0x0e,
+	[20]  = 0x2e,
+	[24]  = 0x4e,
+	[28]  = 0x6e,
+	[32]  = 0x0f,
+	[40]  = 0x2f,
+	[48]  = 0x4f,
+	[56]  = 0x6f,
+	[64]  = 0x10,
+	[80]  = 0x30,
+	[96]  = 0x50,
+	[112] = 0x70,
+	[128] = 0x11,
+};
+
+/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
+static const u8 power_limit_time_msr_to_sec[] = {
+	[0x00] = 0,
+	[0x0a] = 1,
+	[0x0b] = 2,
+	[0x4b] = 3,
+	[0x0c] = 4,
+	[0x2c] = 5,
+	[0x4c] = 6,
+	[0x6c] = 7,
+	[0x0d] = 8,
+	[0x2d] = 10,
+	[0x4d] = 12,
+	[0x6d] = 14,
+	[0x0e] = 16,
+	[0x2e] = 20,
+	[0x4e] = 24,
+	[0x6e] = 28,
+	[0x0f] = 32,
+	[0x2f] = 40,
+	[0x4f] = 48,
+	[0x6f] = 56,
+	[0x10] = 64,
+	[0x30] = 80,
+	[0x50] = 96,
+	[0x70] = 112,
+	[0x11] = 128,
+};
+
+int cpu_config_tdp_levels(void)
+{
+	msr_t platform_info;
+
+	/* Bits 34:33 indicate how many levels supported */
+	platform_info = rdmsr(MSR_PLATFORM_INFO);
+	return (platform_info.hi >> 1) & 3;
+}
+
+/*
+ * Configure processor power limits if possible
+ * This must be done AFTER set of BIOS_RESET_CPL
+ */
+void set_power_limits(u8 power_limit_1_time)
+{
+	msr_t msr = rdmsr(MSR_PLATFORM_INFO);
+	msr_t limit;
+	unsigned power_unit;
+	unsigned tdp, min_power, max_power, max_time;
+	u8 power_limit_1_val;
+
+	if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
+		return;
+
+	if (!(msr.lo & PLATFORM_INFO_SET_TDP))
+		return;
+
+	/* Get units */
+	msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
+	power_unit = 2 << ((msr.lo & 0xf) - 1);
+
+	/* Get power defaults for this SKU */
+	msr = rdmsr(MSR_PKG_POWER_SKU);
+	tdp = msr.lo & 0x7fff;
+	min_power = (msr.lo >> 16) & 0x7fff;
+	max_power = msr.hi & 0x7fff;
+	max_time = (msr.hi >> 16) & 0x7f;
+
+	printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit);
+
+	if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
+		power_limit_1_time = power_limit_time_msr_to_sec[max_time];
+
+	if (min_power > 0 && tdp < min_power)
+		tdp = min_power;
+
+	if (max_power > 0 && tdp > max_power)
+		tdp = max_power;
+
+	power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
+
+	/* Set long term power limit to TDP */
+	limit.lo = 0;
+	limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
+	limit.lo |= PKG_POWER_LIMIT_EN;
+	limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
+		PKG_POWER_LIMIT_TIME_SHIFT;
+
+	/* Set short term power limit to 1.25 * TDP */
+	limit.hi = 0;
+	limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
+	limit.hi |= PKG_POWER_LIMIT_EN;
+	/* Power limit 2 time is only programmable on SNB EP/EX */
+
+	wrmsr(MSR_PKG_POWER_LIMIT, limit);
+
+	/* Use nominal TDP values for CPUs with configurable TDP */
+	if (cpu_config_tdp_levels()) {
+		msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+		limit.hi = 0;
+		limit.lo = msr.lo & 0xff;
+		wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit);
+	}
+}
+
+#if 0
+static void configure_c_states(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+	msr.lo |= (1 << 28);	// C1 Auto Undemotion Enable
+	msr.lo |= (1 << 27);	// C3 Auto Undemotion Enable
+	msr.lo |= (1 << 26);	// C1 Auto Demotion Enable
+	msr.lo |= (1 << 25);	// C3 Auto Demotion Enable
+	msr.lo &= ~(1 << 10);	// Disable IO MWAIT redirection
+	msr.lo |= 7;		// No package C-state limit
+	wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+
+	msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
+	msr.lo &= ~0x7ffff;
+	msr.lo |= (PMB0_BASE + 4);	// LVL_2 base address
+	msr.lo |= (2 << 16);		// CST Range: C7 is max C-state
+	wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr);
+
+	msr = rdmsr(MSR_MISC_PWR_MGMT);
+	msr.lo &= ~(1 << 0);	// Enable P-state HW_ALL coordination
+	wrmsr(MSR_MISC_PWR_MGMT, msr);
+
+	msr = rdmsr(MSR_POWER_CTL);
+	msr.lo |= (1 << 18);	// Enable Energy Perf Bias MSR 0x1b0
+	msr.lo |= (1 << 1);	// C1E Enable
+	msr.lo |= (1 << 0);	// Bi-directional PROCHOT#
+	wrmsr(MSR_POWER_CTL, msr);
+
+	/* C3 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
+	wrmsr(MSR_PKGC3_IRTL, msr);
+
+	/* C6 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
+	wrmsr(MSR_PKGC6_IRTL, msr);
+
+	/* C7 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
+	wrmsr(MSR_PKGC7_IRTL, msr);
+
+	/* Primary Plane Current Limit */
+	msr = rdmsr(MSR_PP0_CURRENT_CONFIG);
+	msr.lo &= ~0x1fff;
+	msr.lo |= PP0_CURRENT_LIMIT;
+	wrmsr(MSR_PP0_CURRENT_CONFIG, msr);
+
+	/* Secondary Plane Current Limit */
+	msr = rdmsr(MSR_PP1_CURRENT_CONFIG);
+	msr.lo &= ~0x1fff;
+	if (cpuid_eax(1) >= 0x30600)
+		msr.lo |= PP1_CURRENT_LIMIT_IVB;
+	else
+		msr.lo |= PP1_CURRENT_LIMIT_SNB;
+	wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
+}
+#endif
+
+static void configure_thermal_target(void)
+{
+	struct cpu_intel_haswell_config *conf;
+	device_t lapic;
+	msr_t msr;
+
+	/* Find pointer to CPU configuration */
+	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (!lapic || !lapic->chip_info)
+		return;
+	conf = lapic->chip_info;
+
+	/* Set TCC activaiton offset if supported */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
+		msr = rdmsr(MSR_TEMPERATURE_TARGET);
+		msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+		msr.lo |= (conf->tcc_offset & 0xf) << 24;
+		wrmsr(MSR_TEMPERATURE_TARGET, msr);
+	}
+}
+
+static void configure_misc(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(IA32_MISC_ENABLE);
+	msr.lo |= (1 << 0);	  /* Fast String enable */
+	msr.lo |= (1 << 3); 	  /* TM1/TM2/EMTTM enable */
+	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
+	wrmsr(IA32_MISC_ENABLE, msr);
+
+	/* Disable Thermal interrupts */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(IA32_THERM_INTERRUPT, msr);
+
+	/* Enable package critical interrupt only */
+	msr.lo = 1 << 4;
+	msr.hi = 0;
+	wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
+}
+
+static void enable_lapic_tpr(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_PIC_MSG_CONTROL);
+	msr.lo &= ~(1 << 10);	/* Enable APIC TPR updates */
+	wrmsr(MSR_PIC_MSG_CONTROL, msr);
+}
+
+static void configure_dca_cap(void)
+{
+	struct cpuid_result cpuid_regs;
+	msr_t msr;
+
+	/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+	cpuid_regs = cpuid(1);
+	if (cpuid_regs.ecx & (1 << 18)) {
+		msr = rdmsr(IA32_PLATFORM_DCA_CAP);
+		msr.lo |= 1;
+		wrmsr(IA32_PLATFORM_DCA_CAP, msr);
+	}
+}
+
+static void set_max_ratio(void)
+{
+	msr_t msr, perf_ctl;
+
+	perf_ctl.hi = 0;
+
+	/* Check for configurable TDP option */
+	if (cpu_config_tdp_levels()) {
+		/* Set to nominal TDP ratio */
+		msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+		perf_ctl.lo = (msr.lo & 0xff) << 8;
+	} else {
+		/* Platform Info bits 15:8 give max ratio */
+		msr = rdmsr(MSR_PLATFORM_INFO);
+		perf_ctl.lo = msr.lo & 0xff00;
+	}
+	wrmsr(IA32_PERF_CTL, perf_ctl);
+
+	printk(BIOS_DEBUG, "haswell: frequency set to %d\n",
+	       ((perf_ctl.lo >> 8) & 0xff) * HASWELL_BCLK);
+}
+
+static void set_energy_perf_bias(u8 policy)
+{
+	msr_t msr;
+
+	/* Energy Policy is bits 3:0 */
+	msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
+	msr.lo &= ~0xf;
+	msr.lo |= policy & 0xf;
+	wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+
+	printk(BIOS_DEBUG, "haswell: energy policy set to %u\n",
+	       policy);
+}
+
+static void configure_mca(void)
+{
+	msr_t msr;
+	int i;
+
+	msr.lo = msr.hi = 0;
+	/* This should only be done on a cold boot */
+	for (i = 0; i < 7; i++)
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+}
+
+#if CONFIG_USBDEBUG
+static unsigned ehci_debug_addr;
+#endif
+
+/*
+ * Initialize any extra cores/threads in this package.
+ */
+static void intel_cores_init(device_t cpu)
+{
+	struct cpuid_result result;
+	unsigned threads_per_package, threads_per_core, i;
+
+	/* Logical processors (threads) per core */
+	result = cpuid_ext(0xb, 0);
+	threads_per_core = result.ebx & 0xffff;
+
+	/* Logical processors (threads) per package */
+	result = cpuid_ext(0xb, 1);
+	threads_per_package = result.ebx & 0xffff;
+
+	/* Only initialize extra cores from BSP */
+	if (cpu->path.apic.apic_id)
+		return;
+
+	printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n",
+	       cpu->path.apic.apic_id, threads_per_package/threads_per_core,
+	       threads_per_core);
+
+	for (i = 1; i < threads_per_package; ++i) {
+		struct device_path cpu_path;
+		device_t new;
+
+		/* Build the cpu device path */
+		cpu_path.type = DEVICE_PATH_APIC;
+		cpu_path.apic.apic_id =
+			cpu->path.apic.apic_id + i;
+
+		/* Update APIC ID if no hyperthreading */
+		if (threads_per_core == 1)
+			cpu_path.apic.apic_id <<= 1;
+
+		/* Allocate the new cpu device structure */
+		new = alloc_dev(cpu->bus, &cpu_path);
+		if (!new)
+			continue;
+
+		printk(BIOS_DEBUG, "CPU: %u has core %u\n",
+		       cpu->path.apic.apic_id,
+		       new->path.apic.apic_id);
+
+#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+		/* Start the new cpu */
+		if (!start_cpu(new)) {
+			/* Record the error in cpu? */
+			printk(BIOS_ERR, "CPU %u would not start!\n",
+			       new->path.apic.apic_id);
+		}
+#endif
+	}
+}
+
+static void haswell_init(device_t cpu)
+{
+	char processor_name[49];
+	struct cpuid_result cpuid_regs;
+
+	intel_update_microcode_from_cbfs();
+
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
+	/* Clear out pending MCEs */
+	configure_mca();
+
+	/* Print processor name */
+	fill_processor_name(processor_name);
+	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+
+#if CONFIG_USBDEBUG
+	// Is this caution really needed?
+	if(!ehci_debug_addr)
+		ehci_debug_addr = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+
+	/* Setup MTRRs based on physical address size */
+	cpuid_regs = cpuid(0x80000008);
+	x86_setup_fixed_mtrrs();
+	x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2);
+	x86_mtrr_check();
+
+	/* Setup Page Attribute Tables (PAT) */
+	// TODO set up PAT
+
+#if CONFIG_USBDEBUG
+	set_ehci_debug(ehci_debug_addr);
+#endif
+
+	/* Enable the local cpu apics */
+	enable_lapic_tpr();
+	setup_lapic();
+
+	/* Configure C States */
+	//configure_c_states();
+
+	/* Configure Enhanced SpeedStep and Thermal Sensors */
+	configure_misc();
+
+	/* Thermal throttle activation offset */
+	configure_thermal_target();
+
+	/* Enable Direct Cache Access */
+	configure_dca_cap();
+
+	/* Set energy policy */
+	set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+	/* Set Max Ratio */
+	set_max_ratio();
+
+	/* Enable Turbo */
+	enable_turbo();
+
+	/* Start up extra cores */
+	intel_cores_init(cpu);
+}
+
+static struct device_operations cpu_dev_ops = {
+	.init     = haswell_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x306c1 }, /* Intel Haswell 4+2 A0 */
+	{ X86_VENDOR_INTEL, 0x306c2 }, /* Intel Haswell 4+2 B0 */
+	{ X86_VENDOR_INTEL, 0x40660 }, /* Intel Haswell 4+3 B0 */
+	{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+	/* .cstates  = cstate_map, */
+};
+
diff --git a/src/cpu/intel/haswell/microcode-M32306c1_ffff000d.h b/src/cpu/intel/haswell/microcode-M32306c1_ffff000d.h
new file mode 100644
index 0000000000..1050969fe1
--- /dev/null
+++ b/src/cpu/intel/haswell/microcode-M32306c1_ffff000d.h
@@ -0,0 +1,1344 @@
+0x00000001, 0xffff000d, 0x03302012, 0x000306c1,
+0x1d84a35e, 0x00000001, 0x00000032, 0x000053d0,
+0x00005400, 0x00000000, 0x00000000, 0x00000000,
+0x00000000, 0x000000a1, 0x00020001, 0xffff000d,
+0x00000000, 0x000014f1, 0x20120330, 0x000014f1,
+0x00000001, 0x000306c1, 0x00000000, 0x00000000,
+0x00000000, 0x00000000, 0x00000000, 0x00000000,
+0x00000000, 0x00000000, 0x00000000, 0x00000000,
+0x00000000, 0x00000000, 0x00000000, 0x00000000,
+0xc2fd8cab, 0x6fa6fb65, 0xaf3ea15d, 0x725f50dc,
+0x658b353e, 0xa1c31b9b, 0xe7243cad, 0xee3e0528,
+0xa19308a3, 0x5b19c4b7, 0x4a1b425b, 0x7d6a74f6,
+0x81624193, 0x3a559605, 0x5475280b, 0xe7319d58,
+0x48624ca7, 0x507af030, 0x3b32d96a, 0x30164068,
+0x5284d2f5, 0x725b2915, 0xf63c9280, 0x44b7c142,
+0xe67ca7b3, 0xd6f163e7, 0xcdf51f3c, 0x41d180a1,
+0xcc3931b1, 0xf7a544a9, 0x7f6bf77d, 0xfc45a45f,
+0xf0985836, 0x652d7e2e, 0x0324b1f3, 0x24b9548c,
+0x7bcae7a5, 0xdcdebf79, 0x27015922, 0x0c83c606,
+0x3d2ceeb7, 0x61c5eec8, 0x6b6899c6, 0x3e500531,
+0xf08bfa44, 0xb304a8f4, 0xcee8f713, 0x2912c786,
+0xfae6c34c, 0xa5292960, 0x7d63e389, 0xaa257a01,
+0x1fb25054, 0x963fc676, 0x5bcb9fd3, 0x58f369a4,
+0xf6e3beb2, 0xa58b5eb0, 0x33c7eba4, 0x37fe8b66,
+0x00714403, 0xf0fd0c4e, 0xaa122996, 0x9a55b184,
+0x00201507, 0xc9fb6e3a, 0x11ab60c8, 0x80ff6e84,
+0xc37aabdd, 0x0fc23175, 0xb0b18c34, 0xf1ec806c,
+0x00000011, 0x2911790b, 0x220445de, 0x3756bc29,
+0xb7080bc8, 0xb610510d, 0xbfe23625, 0xe518d098,
+0x6e99b4b4, 0xe7893eb1, 0x0d149ab6, 0x53e17953,
+0x4b13580f, 0x82e5b176, 0x497d7196, 0xa003bcb5,
+0x912747d7, 0xd825ff22, 0x662988e6, 0x5e5efdec,
+0x614a4f7e, 0xbfa071a6, 0x8a06928a, 0x49fdb221,
+0xfe508725, 0x6071b89d, 0xa2547b82, 0x980e3a87,
+0xd313b690, 0xf83d1ede, 0xe304d098, 0xadcb5f26,
+0xd58e50ae, 0xc1c8f03b, 0x2c35798a, 0x87fe877d,
+0x0a402c34, 0xe2e66f2f, 0x321e15b4, 0xa3b3c9d4,
+0x4e8c1bfb, 0xda693297, 0x7e7a735c, 0x2877c1f3,
+0x246dadb5, 0x475e143d, 0x7621476d, 0x3b8ccfbb,
+0x8f2cc7b5, 0x5f6f8e93, 0x965b70e2, 0x0ba42e43,
+0x9bdbd61e, 0xfe11705c, 0xaecc3b85, 0x1d43b887,
+0xd37a07be, 0x681d104c, 0xf29c489e, 0x8de9e8f8,
+0x95745344, 0xdc9187cc, 0x9f5a3228, 0x9ba5f60b,
+0xd5db93b6, 0x5e6d3487, 0x8356d17a, 0x94d30405,
+0xe9f3173b, 0xda6ea416, 0xa6738342, 0x3b443db1,
+0x518278ca, 0xf34e925c, 0x00710d25, 0x00bddf6a,
+0x06afe3fd, 0xa3ada488, 0x004d3cca, 0x79939fa7,
+0x6a43a257, 0xf3927d5e, 0xe1fd1212, 0x562593fc,
+0x67f0d174, 0x3839c38b, 0x3cca12c5, 0x387f8352,
+0x7045e87c, 0xe165b472, 0xf0a9aac3, 0x88e2c731,
+0x401ad4cc, 0x524b362d, 0x7d216b83, 0x6bc1eff0,
+0xbab1bed3, 0x6c62d049, 0x23363fb9, 0xb02dc51f,
+0x33322777, 0x05347786, 0x4ae86a7d, 0x7e3fd01f,
+0x3d15053e, 0xc1e3b8d3, 0x5c1fe742, 0x4c7a75cc,
+0x2d194497, 0x1446881b, 0xc877a18c, 0x4dedb782,
+0x5b29147f, 0x530a3cc5, 0x21e2f113, 0x42772312,
+0x93f856cd, 0xc3f0eefe, 0xc1b0b4b9, 0x1656ba64,
+0x6068a0e0, 0xb3e7c373, 0x785ae0ac, 0x04d3ef12,
+0x7f1fc4f9, 0x6d06e657, 0xd7923d68, 0x0ccb0f3e,
+0x50a63658, 0x0408630a, 0x452864b1, 0x6dcba513,
+0xc6b02271, 0xd3ea3e2d, 0x4e061ebc, 0x91e7b83d,
+0xbd5663b5, 0xd2ed197c, 0xd89911d7, 0x77559375,
+0x0175f9d5, 0x63c5d8f0, 0x50ef4df3, 0x5d500cea,
+0x434ace15, 0x6f3747b5, 0xc0e15d56, 0x22c17f15,
+0x471a0d73, 0xbbe149e3, 0x63b54989, 0xbe292e53,
+0x81fdfe2a, 0x9fcb7736, 0x5ea8c25b, 0x758da67e,
+0x64369449, 0x86fda1e0, 0x4fcb0fd3, 0xb4bebda6,
+0x0ed42c85, 0x41561212, 0xf770a5d9, 0xdd188df3,
+0x216aa88b, 0x9b101e32, 0x62f16a5e, 0xebcc9e92,
+0x92419a47, 0x9b581102, 0x77714b52, 0x11110672,
+0x5d36f632, 0x9e923f71, 0x3a9041f7, 0x2da8675a,
+0xa9b0f311, 0x0bed2b25, 0xdbe656a6, 0x10f5cb8e,
+0xdefbbaa2, 0x9bd7ad24, 0x88f169af, 0xed621efc,
+0x1831952e, 0x16da28e9, 0x409f94c0, 0x146caa60,
+0x629a22cb, 0x4a458f05, 0xbd08bc73, 0x8c909c25,
+0x06594441, 0x12eede59, 0x93fdd704, 0xe0368b60,
+0x9b1753c3, 0xbdbe2e5a, 0x2df9a57f, 0x9f9c58f3,
+0x6a078218, 0xa1915787, 0x18edde10, 0xf249fa7e,
+0xb6ed1c75, 0xc0ab601b, 0x19b60ce0, 0x2cb00a43,
+0x1edb92ad, 0x434464c6, 0x95f990b4, 0xcad8a584,
+0x6f51cd0c, 0xd2e49283, 0xd5f3100b, 0xdeb93fff,
+0xf9a11003, 0x098d5f24, 0x5ee44c17, 0x4525c531,
+0xaeecd661, 0x6c6eed71, 0x64d78afb, 0x074be2d7,
+0xcab5d351, 0x646f68d1, 0xc3e56ca5, 0x56a9188b,
+0x327f859f, 0x2fdc1097, 0xdde7a664, 0x84bc9f87,
+0xb3e958ea, 0x62759f12, 0xd22f7ba3, 0xc2f35d48,
+0x245b2700, 0xc745e303, 0xc2ce4ab8, 0x7f212b51,
+0xc4e2fd8b, 0x74e19d3f, 0x64d46973, 0x1a7650e7,
+0x84fa8fba, 0x872a28c5, 0xb8d5bb39, 0xaee913d4,
+0x71068d6a, 0x8058a9e7, 0xd3c8d5ad, 0xa1ab9866,
+0x1fe72e51, 0xbfbd2546, 0x7d2e689a, 0x54487eeb,
+0x37b4f05c, 0x50e2c2fd, 0xd139e02a, 0x3e8f32e5,
+0xdf520335, 0x4c1cc8a4, 0xdfc57642, 0x45706a71,
+0x0a9d8080, 0xa15f8acf, 0x44ee3705, 0x28073fef,
+0x7229c0e2, 0x3f3c2e45, 0x84dcb978, 0x5056ea8b,
+0x2976439e, 0xad6bb80d, 0xafefde4e, 0x0c9a60a2,
+0xadfe1faa, 0xbba270c4, 0x82a02b1b, 0xc357de50,
+0xbe813039, 0x5c587027, 0x5b97c5e1, 0xc8f5eac9,
+0x31c0eabc, 0x04cc3a44, 0x3c139e15, 0xa77be6d1,
+0xfe9a0d3a, 0x100beb6d, 0x93354b4e, 0xdbc5181a,
+0x504ba59e, 0xe1e02d60, 0xbe966b54, 0x759ce581,
+0x2479cc6e, 0x10dcfdc4, 0x26dea960, 0xb097ad84,
+0xc5b23428, 0x1043ceab, 0xe7bc23e4, 0x233482a1,
+0x86f17cda, 0x5054f2cb, 0x6c6fed4c, 0xbe57e2c3,
+0x63cbc9f9, 0xa2c0c28a, 0xe7e3c0c2, 0x0fbc9fc8,
+0xd712edb5, 0xe64445a5, 0x4a8ff4a0, 0xb709260b,
+0x1e85db4b, 0xbf795610, 0x4148e521, 0xb6d7b8ef,
+0xcb547ef3, 0xeab3aa17, 0xa6da5440, 0x9fc4ec6f,
+0x3955068e, 0x6a1c4fa4, 0xa9c43a5c, 0x8e689920,
+0x772f96d0, 0x1754416e, 0x1c7d2589, 0x43d3fb04,
+0x021044de, 0xbc5aadf5, 0xba9598d8, 0x84dda1e9,
+0xfb030354, 0xd9c4763e, 0xebc2978a, 0xc86f1a6f,
+0x8fe4f5d3, 0x1955fcd8, 0xbff7a42d, 0x796fe00d,
+0x7d34f977, 0x2b28d705, 0x074415f4, 0xf0149539,
+0x7cf87e36, 0x75e0a02c, 0xea42978a, 0x5b5644c7,
+0x785aaea7, 0x74f8d7c2, 0xccb38924, 0x6fe9c0e0,
+0x7f758138, 0xd2d1d66a, 0xae6bf89c, 0x1681282e,
+0x34cf76ef, 0x752173bb, 0x3475552f, 0x6cb54989,
+0xc22eb443, 0xfb12a8a6, 0x14f14cce, 0xe744005d,
+0x2db6f804, 0x2f2d741b, 0x31a73826, 0x738a1bb3,
+0xeb2e014b, 0x415356a2, 0xa6c3273f, 0xaa661f0f,
+0x9981b9f0, 0xb5aeee63, 0x2530e67a, 0xde5c8244,
+0xcc201d9d, 0x91b1334e, 0x1383920d, 0x917f57d4,
+0x8417e617, 0x0fa322aa, 0xe189d6ec, 0xe8821b30,
+0xc530b1da, 0x22da0b28, 0x7c9d6ab6, 0xdb054639,
+0x02b7a845, 0x1f1afbfa, 0x0fd47762, 0x42dd9053,
+0x1a858a0f, 0xa5518ac6, 0x9a090813, 0x3aa41cb9,
+0xb424f20c, 0x46b7ec99, 0xfc81af92, 0x7ad95854,
+0x27272dec, 0x4662d252, 0xa7058894, 0x0557c937,
+0xb1306750, 0x1f130309, 0x6b14a1e2, 0x3870776a,
+0xb48df3e0, 0x368c8fdc, 0xa3a99e4f, 0xf5c2ef2d,
+0x4eb70135, 0x1997f993, 0xfaf2e90d, 0x39536638,
+0x594782f8, 0x155a9367, 0x4ea58e8a, 0x71bc8691,
+0x3f654b13, 0x8a745d7f, 0x9f4551a4, 0xd01a1c9d,
+0x0316afbc, 0xce48e29e, 0x5edcb727, 0x97751ce5,
+0x044bed10, 0xbfae5a76, 0xdd1bc019, 0x05f6c7e4,
+0x34c3ff13, 0x488315b8, 0x523ceea3, 0x0dd5f7a5,
+0xa24fd70d, 0xce8eb6fc, 0xd191a719, 0xd295651b,
+0xa909f533, 0x90a6eb7d, 0xd1bfc50b, 0xe5f090ae,
+0x73d42e99, 0x78195762, 0x8b674cfe, 0x0a440728,
+0x8498629e, 0xc15b5e68, 0x938bea09, 0x8eb80202,
+0xb942bdc3, 0xe9753f82, 0xf7584a4e, 0x3c1179d3,
+0xfe72f3d9, 0x1efb9911, 0x12a89365, 0xbbdf1873,
+0x3cce4841, 0x3d364836, 0x2494446a, 0x6f9331b0,
+0x84de569d, 0xa7dca221, 0xb5163bb6, 0x8d854e44,
+0xbbf67468, 0x3920ca2c, 0x4873d2dc, 0x4dedd222,
+0x0237d22e, 0x2df26e66, 0xe6f96230, 0x45061a66,
+0x56733f4d, 0xdb22eb68, 0xc1e2450c, 0x5bb43be4,
+0x6f509c3c, 0xd100b77a, 0xa0189b88, 0x16557852,
+0x0d3a9b92, 0x8e16aab5, 0x2538c82a, 0x465d5249,
+0x96bea7dc, 0x42ae8539, 0xa2438010, 0xaa536691,
+0xc062277c, 0xcfeb1744, 0x3f25a727, 0x90f0f357,
+0x5bdf7d9d, 0xb3b36fdb, 0x7b26e697, 0xfb79b618,
+0xfd179d0d, 0x130a40d6, 0xc58d1efc, 0x17ed54d3,
+0x5dd7151b, 0x160484a0, 0xbd82d590, 0x882ac7f2,
+0xb1425923, 0x952d3901, 0xf8669d56, 0x306eb2c8,
+0x753954c8, 0x4e91e2e2, 0xc657defd, 0x08d7ca9b,
+0x4eb1dea1, 0x1f01f85b, 0xc3a5a432, 0x56a1997b,
+0xd38331ef, 0x4e58f717, 0x2d5bd837, 0xec41c072,
+0x725ddcb0, 0x21a094ab, 0x6af39856, 0xe5beb8f5,
+0xe594a652, 0x8349f482, 0x64b6b627, 0x158d3920,
+0x1b3b4932, 0xe5d9e247, 0x5283ace8, 0x53c320b6,
+0x92582238, 0x37ce2d4f, 0xc24a5564, 0x94762d9b,
+0xa2f35d7e, 0x2f6b9bdd, 0x08064b0a, 0x921d7fbf,
+0xb4af0273, 0xf88182d3, 0x6cb389e9, 0x97ace86d,
+0x9636e118, 0x70e0b558, 0xde28b6a8, 0xdec4de13,
+0xb58f98d0, 0xc57917ff, 0x3c76eaf9, 0xb441d1b8,
+0x34623de5, 0x1851db1c, 0x1e5943e4, 0x640d56b7,
+0xeda5eae5, 0x97b9b745, 0x9a13d5ab, 0x1af48c92,
+0xb436bc90, 0x593cad9e, 0xdbff3108, 0x461d0b32,
+0x4432bcc4, 0x9ee3dce7, 0x558dcd2d, 0x84092f36,
+0x37321f94, 0xdace9236, 0xea8a0fcc, 0xed62e7db,
+0x86642ab9, 0xd9512038, 0x50cb9e7d, 0x2d8c3ac8,
+0xa97ad442, 0xaac479b3, 0x24c08549, 0x61af5a52,
+0xd30aadcc, 0x216f8681, 0xb2ec2127, 0x343eab52,
+0x05515c8d, 0x3a1c7625, 0x1d053385, 0xa30ebbd1,
+0x779813a0, 0xe18b85ac, 0xee7e4907, 0x9a0c0940,
+0x8cc8a461, 0xfd82d0b3, 0x807b1f95, 0x82cbd8d8,
+0x4cafb4a3, 0xabaa2eca, 0x0759e4b8, 0x41a6d782,
+0xc5d100de, 0x02482d4c, 0x80f9f6e8, 0x7999ea4a,
+0x1d9dafa8, 0x622e6df7, 0x0dbbe21c, 0xf031d31e,
+0x6bfa2bf2, 0x24e1064b, 0x64b4c4b2, 0x198372c4,
+0x071f0e1a, 0x2fe6dd57, 0xf2085803, 0xa790c560,
+0x498c10ae, 0xde8b91d2, 0xcc502267, 0xb934850d,
+0x9e7f555b, 0x3957038b, 0xa76e1b11, 0x0edecf31,
+0xdc32e2d6, 0xefd01b56, 0x4602aa57, 0x0768d5d9,
+0x492f2838, 0x6454a32a, 0x935b4937, 0xbbb3c8d2,
+0x49dc355f, 0xb091e3a7, 0xdf1c6465, 0x997bf9f2,
+0xe4bd3100, 0x5a3aae7e, 0x74d90b7e, 0x11b18734,
+0xcd157ca9, 0x59a8cd4a, 0xef21b531, 0xdcbeca37,
+0xe3b19a26, 0x9476ad7d, 0x2124a922, 0xc665d502,
+0x5e92c2a2, 0x6924bead, 0x67093ddc, 0xfd87b7e5,
+0x14627489, 0x510b7d85, 0x252b01f0, 0xeef9f8fc,
+0x4f023627, 0x5029536d, 0xe32c9d6f, 0xb160d734,
+0xc5fd8019, 0x8c52b162, 0xb62016a6, 0xe174e01f,
+0x63255ea4, 0x8e51131f, 0x5b13c027, 0x403919ff,
+0x8d819aad, 0xbcf4cf23, 0x42ee0de6, 0xadd49f81,
+0xa32a6443, 0x19513428, 0xc97b0288, 0x65bb31e4,
+0x6ab26c92, 0x21fa3a90, 0xa4ea6d91, 0x80d3ec0c,
+0x716c638e, 0x9cb8c079, 0x779cc058, 0x45c96df2,
+0xd94be27b, 0x3b88a219, 0x7d55a5c4, 0x9bfb7c09,
+0xad919f74, 0xa8de3c9d, 0xd4532b3f, 0x15b748af,
+0x9c6d31b4, 0x9e365eae, 0x0683025a, 0x996d72a7,
+0x7ca75780, 0x4288af50, 0xa9762d9a, 0x5a7abe79,
+0x798c9cb8, 0x9f9a6918, 0xeadef40c, 0xdb572477,
+0x05fe5a39, 0xcce4d24e, 0x9df361c6, 0x40a3e766,
+0x4619fc70, 0xc00f502e, 0x4f413317, 0x5afb7c4f,
+0x95ff6889, 0xb197aff5, 0xb4a80cd8, 0xb25ad853,
+0xff1697a5, 0xb7ef18d0, 0x63e93034, 0x1fafe103,
+0xda76fbae, 0x0df20325, 0x1bb2778f, 0x2522e0d7,
+0xd528a486, 0x6d5a718d, 0x6598bda5, 0x5edbcf69,
+0x03fd42b6, 0x764907a0, 0x5581f54d, 0x70cd644d,
+0x8880de51, 0x2ffd0f8b, 0xba8427c5, 0x26a12c5d,
+0xb4a7815e, 0x4b501fa2, 0xdde2294a, 0x2a6df749,
+0x768e19cc, 0x37045304, 0x3f779c4f, 0x214bec70,
+0x2105f3ed, 0xa13c4520, 0x6eaeeb9d, 0xf55137fe,
+0x0db8fd36, 0x90570927, 0x7c51a071, 0x3acd1201,
+0x471a504f, 0x8f8b4dc8, 0x5fbc5277, 0xd11763c6,
+0x3a59ebf7, 0xfae42348, 0xf8ce6b40, 0x32830204,
+0x354ff5f1, 0xf0e472bc, 0xe9086fb4, 0x7a589a9b,
+0x5039355b, 0x8abf9782, 0x21079bf5, 0x99bcdedd,
+0xef43a037, 0x118be1c1, 0x1b345c8c, 0xcecb2ced,
+0x7d5dd66d, 0x234d95b0, 0x251a8770, 0x8a25574d,
+0x5fafa8ed, 0xe607987a, 0x4a8b244b, 0x819b2037,
+0xc9938834, 0xb8d5dd83, 0xa942c68f, 0xc1cdca9e,
+0x179aae1c, 0x8588faed, 0xd56205a0, 0x4a0d1430,
+0xcbecbab0, 0x24afcc1f, 0x10fcf1a6, 0x46c7d891,
+0xd8f2c33a, 0x64568220, 0xcee3c2cb, 0x0a0e2904,
+0xa619ad7c, 0xaf912f17, 0x4d8b8901, 0x628e08fb,
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+0xc17a0e79, 0x57ad9c76, 0x0878421f, 0x76abf479,
+0x6cd79141, 0xae93e02c, 0x5d1e9f22, 0x4f7ed641,
+0x65d1a70d, 0xff16ced7, 0xa5198150, 0xa39ae34c,
+0xd8f496b7, 0x1e4d8c6f, 0xd3328ca6, 0x51fbf9e9,
+0x3b6f0034, 0xd43985dd, 0xed545c51, 0x6891a9f2,
+0x37914b34, 0x95aee6ca, 0xbe3e88f1, 0x8c081851,
+0x0334976b, 0xe7976cfb, 0xd6a99830, 0x32ca2d18,
+0xcdaa8600, 0x176d3707, 0xf41b2924, 0x498ee4d4,
+0xc4fbc8ba, 0x0a7eeb99, 0x03d12baa, 0xd53c4127,
+0xe4a20d1d, 0x21e9f27b, 0xc93b747f, 0x81362c8e,
+0x30d4511e, 0x50914eec, 0x1ec00ec6, 0xe0cda769,
+0xb6d056f1, 0x7b2a2618, 0x7a466001, 0xf5673969,
+0xa45795d5, 0x2c3a4459, 0x19d00f28, 0x86cbb72c,
+0x4f892d8d, 0x932832e5, 0x17ef120c, 0x5738d6a4,
+0x950a91cf, 0x763994f3, 0x5a639cf8, 0xbfadf3c1,
+0x8b6336bc, 0x8cb0587e, 0xbc4d0a5b, 0x242a504e,
+0xcfa99d25, 0x641613cd, 0xb8c20ab0, 0x28509bae,
+0x7938b4ee, 0x3116aa0c, 0x7fd6eb15, 0xda754baf,
+0x3016ee4a, 0x276b8de2, 0x4006455a, 0x85908f25,
+0x3498ab4b, 0x9b0e4ab2, 0x721e80bb, 0xb23172e7,
+0xeb850a12, 0x06419469, 0x8d11ed10, 0xc173c146,
+0x23566335, 0xe4f77d1c, 0x571e7886, 0x9ba798b4,
+0xa1c4afba, 0x2329fb10, 0x1c5ab56a, 0x180702d2,
+0x21742711, 0xfb615747, 0x0a0e6e6a, 0x418b2481,
+0x25f5923b, 0xb6017e44, 0x91280c56, 0x2c4d5cfc,
+0x735d765e, 0xea7840c3, 0xbe0e25bc, 0x0665ae5a,
+0x588f7c0a, 0x0554df7c, 0x20a71000, 0xcef418cb,
+0xa6a2e1d5, 0x9a482e57, 0xb6ce74be, 0xd9017756,
+0x5d9a09dc, 0xbc30331f, 0xdd7f356c, 0xe0b9642b,
+0x9b104272, 0x7ff96c11, 0x7d196ee9, 0xea09435c,
+0x04c3c4dd, 0xa445e93f, 0x53859456, 0x409d4d7d,
+0xa834e183, 0xb5e7ae44, 0xb9ecd12a, 0x97d374c5,
+0x9da5593e, 0xfbdc5bc8, 0x421e59ce, 0xf1073ec1,
+0xe8f16243, 0xc8133042, 0x37072879, 0x74b067ce,
+0x97a29089, 0x827cde7c, 0xbf1ee463, 0xf1207288,
+0xd264239d, 0x889bb5ed, 0xdd26ad0a, 0x419c9029,
+0x837a1d85, 0xa92918e0, 0x4a7caa45, 0x7c718f07,
+0x9a9a8ac1, 0xb58458d5, 0x38b1d8c7, 0x7a7528a5,
+0x6e809471, 0x39c4505a, 0x8b2de89f, 0xdd488911,
+0x7c71475b, 0xbccec2ce, 0x1f0a3cb7, 0x368089e1,
+0xf546c873, 0x98915f67, 0x3cde685e, 0xd7af539d,
+0xd5345ef9, 0xd89fe631, 0xaf68e6db, 0xd77ce130,
+0xf4eb9eb9, 0xb0b90b10, 0x52221daa, 0xdef2fba6,
+0x732733df, 0xf3fc3675, 0x6cf5f49c, 0xed8d944c,
+0x08798c96, 0x3d586cec, 0x52887076, 0x80038f98,
+0x7802751a, 0xfe6a883e, 0x8e4246e4, 0x9ad0b1b2,
+0xdf7b7a6f, 0xa6d43d10, 0x60c3bc89, 0xa316d96e,
+0xadbe1f03, 0xc5b7f11b, 0x8c02d1f8, 0x71a3a455,
+0x8c934d22, 0x186e3dfa, 0x325987ca, 0x30153b09,
+0x89bea29f, 0x611f897e, 0x8b912009, 0x272304d5,
+0x34a0e222, 0x1f36a1a4, 0x60d0ba6d, 0xb84e9869,
+0xb1770707, 0x27d7bfd6, 0xbd82f41e, 0x1ff5fcb9,
+0xc39b3c66, 0xafc85927, 0x9fa472db, 0x4ffc0fc6,
+0x459dbdc7, 0x4a3ba7d8, 0x7e4e59ce, 0x6906e461,
+0xad09ddec, 0x3fb7fd36, 0x92471185, 0x9c3a1a56,
+0xd2729393, 0xa797d207, 0x4c40e3a0, 0x26ce5f64,
+0x235ed861, 0x27079b15, 0x78da2416, 0xa014962f,
+0xa9071722, 0xbe329d45, 0x7ac167b2, 0xac775c3c,
+0xd0fe38c3, 0xafc1ca30, 0x15092916, 0xafd01d7f,
+0x376b90ee, 0x85976f7f, 0xe3194c27, 0x82315ecf,
+0x04c70174, 0x2dd7a902, 0x9cb660a1, 0x4b73ef57,
+0x3fdc9634, 0xd154fd0c, 0x502a76d7, 0xfbcc0f26,
+0xec92bfbc, 0x5efc8336, 0x4d3aa101, 0xa7ae5fa7,
+0x45b01e93, 0xb8ad3946, 0xd25e6474, 0x4be730ac,
+0x318f881c, 0x2cdb700e, 0x17fa65e0, 0x5a2c28ba,
+0x7bf74562, 0xdf569a0a, 0x70b73d39, 0xbffcaae1,
+0xf0cafc19, 0x05d7216b, 0x7fe52fbb, 0x20cdaf91,
+0xbb997e15, 0xd33de063, 0x740f84ac, 0x99f8df83,
+0xca7873df, 0xb3c4b404, 0xa9f6ef04, 0x1e3ca888,
+0x354da772, 0x6abcf01e, 0xfb31b8f9, 0x136dc30f,
+0x07b4fb3e, 0xfe02c93a, 0xf6c768ef, 0x61306415,
+0xef9b2e91, 0x5916f671, 0xc98dfcd6, 0xb9890c29,
+0x7c1991f5, 0x689b34f1, 0x89eaa10e, 0x898d2587,
+0x4f91aed2, 0x1de48e3a, 0x68484360, 0x26300f3e,
+0x3ae22620, 0xae9cb796, 0x8261da0d, 0xa1073a54,
+0x1d20fc8c, 0xfbcac33b, 0x24da2296, 0xa17b56ac,
+0x77024c68, 0x06154395, 0xa86eadcb, 0xaa6d0cd3,
+0xaea96f37, 0xc17bde9e, 0x40e406f3, 0x390335a3,
+0xbe334721, 0x014e2f50, 0xb3c63af3, 0x7f415e47,
+0x5c1fe00c, 0xebd013aa, 0xe732d15c, 0x6acdd540,
+0x898eeb9c, 0x860ec697, 0x6a84a05a, 0x5bf0ecee,
+0x85112a74, 0x43969340, 0x1cde8ced, 0xfb5a0990,
+0x5b7c75d6, 0x288328b6, 0x65fb99da, 0x74c98ebd,
+0xf60dd7a8, 0x022e3ada, 0x6c230086, 0xb037ba3b,
+0xd3d836cb, 0xdca668ca, 0xb6b3aba3, 0x83c3ef0b,
+0x6710928d, 0xfdba4378, 0x03bac767, 0x54cec351,
+0xd2e3b9be, 0xb6aa98ef, 0xdf287538, 0x61790fe1,
+0x533a12e2, 0x33dbcb67, 0x0cc8f931, 0x810bd09f,
+0xc61af214, 0x63b5cd33, 0x7ac2b448, 0x33f4d1ba,
+0x0a50bae5, 0x27602505, 0x16aa586c, 0x920e6571,
+0xccf0c6b5, 0xc51f8395, 0xc35a6439, 0xc4614d06,
+0x8ef9873f, 0xa487ff48, 0x2a99c506, 0xc413ac23,
+0x1fc82df5, 0xbbccd6ff, 0x5aa56325, 0x73e8e3cb,
+0x7eedce1b, 0xf8e24d26, 0xe2c61c5f, 0xb70c0f64,
+0x3a05e507, 0xb5e37580, 0xa7e5ef1f, 0xdd612535,
+0xfd2010ea, 0xcd02b51e, 0xbeda36f3, 0x4cf61f22,
+0x23b69f0b, 0xbbf35eb3, 0xd9c41880, 0x04860fd9,
+0x61333ce9, 0x87722946, 0xc952b651, 0x52941d10,
+0x64856595, 0xdfbde2f4, 0x1eff8930, 0xc214baa7,
+0x0e100773, 0x1f7de202, 0x48401e8c, 0x631ebe0a,
+0xe4f74144, 0x410bee40, 0xdafcffda, 0x9863fbc3,
+0x29ff025d, 0x73befee2, 0x31a25def, 0x55bdc13e,
+0x6953848a, 0xdf9e9126, 0x6fc7543d, 0x2bda5cad,
+0x408ad459, 0xceef5177, 0x6ce8e470, 0x5b08a3f3,
+0x239e9e13, 0x235bef5d, 0xbf7faee7, 0x695f90a4,
+0x397e39e9, 0x60b05c26, 0xf8daa802, 0x86239a3e,
+0xcf5fbe6c, 0xaf29ce64, 0x0e69bd79, 0x9b81c4dd,
+0x60773dc6, 0x83a3641a, 0x6a96a4a2, 0x1dee9161,
+0x11b74f04, 0xac0d174c, 0x9e684e45, 0x685d962c,
+0x01b4f8c2, 0xb54dcc23, 0xd186b0c4, 0x9a4576e2,
+0x385ba279, 0x3bf1ad85, 0x1363b23b, 0x5457c13b,
+0x3c8d4c14, 0x8c7571d4, 0xf24ee9ff, 0x8a6a1e90,
+0x68652e59, 0x66f852a9, 0x9f343cee, 0x11a6c25a,
+0xabe276b4, 0x62de8e07, 0x9cea453b, 0x591ddc6e,
+0x2aa6060c, 0x99bbbe41, 0xd5834d17, 0x6544c474,
+0xb6506fd3, 0x05a01209, 0x9b5a45cc, 0x2d526acb,
+0x11a46a14, 0x6baf5a76, 0x7aef0244, 0x38fb57b5,
+0x25dc57f9, 0x73cf77b3, 0x5ed90dc1, 0x221a5a4f,
+0x1c3af5dc, 0x37208f35, 0xb5a371fe, 0x90a97e72,
+0xa60cf62c, 0x9facab7b, 0xfcdb4b5b, 0x8d5eaba9,
+0x0970fe84, 0x4e1da0b8, 0x98ac07f2, 0x68910cf6,
+0x69c9ee67, 0x9ec0a0a2, 0x393b0a64, 0xf99cba85,
+0x0f176323, 0x248ad952, 0x231f3f6d, 0x7afa35c8,
+0x58717c92, 0x459dceed, 0x126fb328, 0x8416ff53,
+0x4363e154, 0x09515f00, 0xdf5f6055, 0x4501a65e,
+0xd2aba10d, 0x18bd34f9, 0x8ed05a12, 0x0914f019,
+0xf5a9bca7, 0x666f2a0b, 0xee47bf3a, 0x05c77428,
+0xfc71f5ec, 0x904420cd, 0xa81a95b6, 0x9d9f4281,
+0xc9f7dfbd, 0x0db6e8a2, 0x4b240a04, 0x5b32b78b,
+0x2e25b8ab, 0xe3f21033, 0xa17153be, 0x01443202,
+0x716e8f06, 0xbd10fe83, 0x3b7c67a6, 0x6be45473,
+0xa68764d2, 0xf0ef7e0c, 0xe09fbb4c, 0xf385cbe1,
+0x0517ae28, 0x0f681494, 0x0b69ff77, 0x98bea1d5,
+0x8d4cc9f3, 0x7a2c336f, 0x717b846c, 0x660dfc4c,
+0x1cff8fec, 0xf44a5a8c, 0x6d1405b8, 0x037e0d37,
+0x9b0690e6, 0x91bf5f3b, 0xf14006da, 0x9357fcc7,
+0x0a604416, 0xb8d97f74, 0x380a5792, 0xd622b034,
+0xf2bff4ff, 0xf8260df2, 0xd980ec61, 0x11456e63,
+0x90ea6625, 0xa58b58d9, 0x06dcf3f9, 0xca265c6e,
+0x644cf469, 0x6d3d3132, 0x67b895dd, 0x5f73ed21,
+0x1bbff0c1, 0xdb67e1db, 0x3469b906, 0x472a494c,
+0x11ce3913, 0xcc40ba06, 0xd1f9ed8d, 0x199376ce,
+0xf1c187dd, 0xe968a2f3, 0x99df8136, 0xc6cd2f5c,
+0x0736cf99, 0x67735a24, 0xe3289e49, 0x98993b8b,
+0x83c6a63d, 0x82446feb, 0x32990572, 0x69fce8f2,
+0x54a4e7b4, 0x082b55c8, 0xced04021, 0x36b4f399,
+0x85518b8e, 0xb83a5554, 0x1d98f4c6, 0x690cb8e8,
+0x680e81e2, 0x0d423679, 0x956384a8, 0x3b29939c,
+0xe1141bea, 0xed6d5c01, 0x6a58f172, 0xb576344d,
+0xd1e17d08, 0x3127733d, 0xb4c6c1a1, 0x5398cfb2,
+0x132ab640, 0xa43a7405, 0x055c2baa, 0xf4cb5f56,
+0xb91aa44b, 0x81908a6d, 0x55f43555, 0x483536e4,
+0xd7e14a06, 0x5f4266fc, 0xce695d31, 0xd3b2e86b,
+0x2c366b7f, 0xe8eb35f1, 0x1af96dd9, 0x00d5d0ba,
+0xba0bb8a8, 0x7e113800, 0xf029dcee, 0x0ce1842b,
+0xc71f0e6a, 0xca886800, 0x8d72850a, 0x153c3359,
+0x9770b744, 0x9c90f074, 0x0c273436, 0x881dee82,
+0x59debdd0, 0x4d67544f, 0x2502ec3a, 0x2359a6b6,
+0x3ad8cf3a, 0x5549f7cc, 0x1f6b6cf6, 0x734114d4,
+0x382e6e4e, 0xdaf50df3, 0x32d757f4, 0xb9a96957,
+0xb4914a40, 0xee0998ed, 0x06579e7e, 0x89099671,
+0x774f1ae0, 0x13dcf84b, 0x18f6bbb2, 0xec99b125,
+0x47583aef, 0xb7be0893, 0xfb180296, 0x4c444071,
+0x56c57e61, 0x413d3c6d, 0x76fe9f90, 0x5ab978b7,
+0xbf1d8866, 0x83756707, 0xbe70a35f, 0x0ffbc112,
+0xd92fe756, 0x69301a19, 0x86adc471, 0xdb9d616d,
diff --git a/src/cpu/intel/haswell/microcode-M32306c2_ffff0003.h b/src/cpu/intel/haswell/microcode-M32306c2_ffff0003.h
new file mode 100644
index 0000000000..627297fed0
--- /dev/null
+++ b/src/cpu/intel/haswell/microcode-M32306c2_ffff0003.h
@@ -0,0 +1,833 @@
+/* 0x306c2 built on 07102012 */
+0x00000001, 0xffff0003, 0x07102012, 0x000306c2,
+0xaf97f1f8, 0x00000001, 0x00000032, 0x000033d0,
+0x00003400, 0x00000000, 0x00000000, 0x00000000,
+0x00000000, 0x000000a1, 0x00020001, 0xffff0003,
+0x00000000, 0x00000cf1, 0x20120710, 0x00000cf1,
+0x00000001, 0x000306c2, 0x00000000, 0x00000000,
+0x00000000, 0x00000000, 0x00000000, 0x00000000,
+0x00000000, 0x00000000, 0x00000000, 0x00000000,
+0x00000000, 0x00000000, 0x00000000, 0x00000000,
+0xd3ad173b, 0x3a858e7c, 0xbd2a6573, 0x33af95ab,
+0xac27ec24, 0x043a80dd, 0x78c629bc, 0xd3b160e0,
+0xa19308a3, 0x5b19c4b7, 0x4a1b425b, 0x7d6a74f6,
+0x81624193, 0x3a559605, 0x5475280b, 0xe7319d58,
+0x48624ca7, 0x507af030, 0x3b32d96a, 0x30164068,
+0x5284d2f5, 0x725b2915, 0xf63c9280, 0x44b7c142,
+0xe67ca7b3, 0xd6f163e7, 0xcdf51f3c, 0x41d180a1,
+0xcc3931b1, 0xf7a544a9, 0x7f6bf77d, 0xfc45a45f,
+0xf0985836, 0x652d7e2e, 0x0324b1f3, 0x24b9548c,
+0x7bcae7a5, 0xdcdebf79, 0x27015922, 0x0c83c606,
+0x3d2ceeb7, 0x61c5eec8, 0x6b6899c6, 0x3e500531,
+0xf08bfa44, 0xb304a8f4, 0xcee8f713, 0x2912c786,
+0xfae6c34c, 0xa5292960, 0x7d63e389, 0xaa257a01,
+0x1fb25054, 0x963fc676, 0x5bcb9fd3, 0x58f369a4,
+0xf6e3beb2, 0xa58b5eb0, 0x33c7eba4, 0x37fe8b66,
+0x00714403, 0xf0fd0c4e, 0xaa122996, 0x9a55b184,
+0x00201507, 0xc9fb6e3a, 0x11ab60c8, 0x80ff6e84,
+0xc37aabdd, 0x0fc23175, 0xb0b18c34, 0xf1ec806c,
+0x00000011, 0xd7ac04bd, 0x43c47748, 0x8b4d3b0e,
+0x37292b60, 0x88f69665, 0xe29ecca3, 0xea58d4ff,
+0xc510039d, 0xcf90334c, 0x72613f09, 0x068fb362,
+0xba19d1a8, 0xba0b5f4f, 0xf98ea81f, 0x5a149d3d,
+0x46b8569a, 0xb1a7bf13, 0x20264bae, 0xd0254070,
+0xfbf03ebe, 0x4d257a4c, 0xc6b129cb, 0xe94b010f,
+0x1a1bc256, 0xb0627b4d, 0x5d884902, 0x8992f09a,
+0xa248ba5d, 0x774ce24e, 0xd18a8e9f, 0x308c2101,
+0x654f9f54, 0x48860d0b, 0x20d42d6b, 0xcb21b8af,
+0xdae28e34, 0x9eadb1ef, 0x0f63d558, 0x65852c08,
+0x2fc9d718, 0x4a7b327e, 0x25da4117, 0xbc9f1a1a,
+0x330b88fa, 0x4e88ca00, 0x93a206cf, 0xf1108fa5,
+0xb4f994bd, 0xa2788822, 0xf3bd71b9, 0x7a095358,
+0xe9ee1f78, 0xdedfb10f, 0xfd805db4, 0x0ad7ecfd,
+0x73f6c7f9, 0x05ea6af9, 0x92d19d64, 0x325b6143,
+0x65446f10, 0x9d82d963, 0x4e9968d4, 0x9e7f5375,
+0x3e4a36df, 0x73c4f910, 0x6042ebab, 0xdaf76fed,
+0xda4fa82e, 0xf15de75e, 0x40ddfb97, 0x9bc1c7ca,
+0xfd58d90a, 0x4b37269e, 0xf534da12, 0xc9ffbb4d,
+0x05d71f15, 0xba506b7a, 0xfb90e223, 0xf46faf4b,
+0x0ad694ba, 0x0dc0b857, 0x5b8df4c2, 0x5d6f7f13,
+0x32eecd90, 0x7f7f272b, 0x271f0bdb, 0x25bd7819,
+0x25f19df4, 0x2a435865, 0x1a28201b, 0x26d186fe,
+0x6abad792, 0x3b902d01, 0xf4dbf9c6, 0xe883fb9f,
+0xce6233f7, 0xcf34fdc2, 0x8ed7096c, 0x05ad22a6,
+0x20ead5b2, 0x9af8e44b, 0x9cbbeb21, 0x1970c013,
+0x61089e83, 0x41eb77a3, 0xd05867ab, 0xf6409d11,
+0xac007c25, 0x97d78d4b, 0x5af38c3f, 0xed5a972c,
+0x3561d959, 0x824b8761, 0x9fc69de4, 0x3094e8b8,
+0xcfb81787, 0x35832e8f, 0xa320931f, 0x2b044e78,
+0x2ba04a27, 0x87ada1c7, 0xd61b0f91, 0x86f2c5dd,
+0xd4a2caa3, 0x6e71cdeb, 0xef8b87fb, 0x329fc815,
+0xcd69b570, 0x25c92597, 0xb81139a6, 0x84b35f2c,
+0x960bbbb2, 0xd4a1b46f, 0xaa9bd40e, 0x129f9cfc,
+0xf2775921, 0xf69c866a, 0x8927ae0c, 0xc297d25f,
+0x22eaecba, 0x9289f366, 0xda25f880, 0xaefaf3c2,
+0x231fa1c3, 0x022230dc, 0xe4e7f071, 0xf9b77e6b,
+0x48cf1fde, 0x1b82d4f9, 0xcf7d150a, 0x5ef46aa1,
+0x41ef98b5, 0x45bc0d43, 0xbd2c471b, 0xf227d6ed,
+0xfa8070d6, 0xba48ef91, 0x709e2371, 0x0648d521,
+0xecb6313b, 0x1823d7e0, 0x88e88325, 0x668f220a,
+0x407f5f89, 0xcb3bc4b3, 0xec901d63, 0x1120b657,
+0x49b14178, 0xf467509b, 0xe6d035e0, 0xdee2b2ec,
+0xfd4b20a2, 0x69866d1f, 0x1bcfeebf, 0x7b76df63,
+0x24f86a8b, 0xd2a928e4, 0xab66fc07, 0xb52b4147,
+0x35d8ce1a, 0x6c12eece, 0xbc51eda2, 0x1083aaf6,
+0x554048f0, 0x3a610276, 0x162dbf03, 0x9eed4230,
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+0xcc2a373f, 0x165f38c4, 0x02b8add5, 0x61e47815,
+0x116c57d2, 0x6b67c50f, 0xdd8ae800, 0xc1f6a03c,
+0x8309af5e, 0x0f2c5b63, 0x779d5019, 0xb616b270,
+0xc1a1a1b7, 0x1b1b2661, 0x9927b0fd, 0x07f5f1d1,
+0xba22b9fa, 0xa54d7eec, 0xe05cc15f, 0xba960b08,
+0x2ff8a219, 0x5dd09b73, 0xd86605e7, 0xcaeeacb2,
+0x85a31962, 0x3b921d1f, 0xb2826458, 0x0a1aaef5,
+0x2c5ff654, 0xa33d31b0, 0x4ccda15b, 0xcb319e52,
+0x1122a597, 0xb843bfe7, 0x458a32ad, 0xa48e3501,
+0x6ce0492c, 0xac6df16a, 0x6d1161ef, 0xaebf8bad,
+0x161e6c19, 0x7b7d7409, 0xed09d861, 0x7f6b3ff7,
+0xceb74158, 0xf4af4d98, 0x243cbfa2, 0x431ac884,
+0xa250d7e8, 0x45ba8c96, 0xcbb8328c, 0x3e0025c6,
+0x2212bd7f, 0x0b8645d7, 0x982bb115, 0xbb16d79e,
+0x6d017fb3, 0xf19eda38, 0x96fa13a3, 0x50c9c6c4,
+0x0cde0a16, 0x7d0231e3, 0x50e520fc, 0x068841c0,
+0x79c5b7e3, 0xd05c7287, 0x9d24268c, 0xd6c86529,
+0x74dd5f2d, 0x5875e945, 0x20a2f564, 0x2e33fce9,
+0xa30b53ec, 0x3de3269c, 0xd90773fc, 0x3fe0fd4e,
+0x0372211b, 0x759889b9, 0xc11357b0, 0x53ba3a32,
+0xbd5b3f61, 0x6f0d8aba, 0x0a1ce4e0, 0x83a2f819,
+0x5fee403b, 0xe56905e0, 0x4c3ecbc2, 0xf4942d75,
+0xcc765225, 0xff18d629, 0xeedbb175, 0xef0be9c1,
+0x3811969b, 0xfa2708be, 0xa06bd4f8, 0x097a718c,
+0xcadf6135, 0x41990cf1, 0x5198f34c, 0x88529cb7,
+0xe4791ed1, 0x744ad621, 0xd015a1b1, 0x91a1d8eb,
+0x5e6ef569, 0x9ebfe89d, 0xc50425e9, 0x27d6f47d,
+0x0b0f3360, 0x84ed39bf, 0x49f4a559, 0xd6270a6a,
+0x0da209bc, 0x99ca1cc2, 0xa58d1182, 0xae3b8885,
+0xef5e7449, 0xe4f73901, 0x4e4117bd, 0x5375cfca,
+0x4769238c, 0x2ada151b, 0x5aa7626e, 0x408d6d79,
+0x5c820b16, 0xdf021ef9, 0x24e41301, 0xa483c2c8,
+0x35cba219, 0x299f9c47, 0x394b6fbf, 0x1c1e4ee1,
+0x7ed4a725, 0xa5198ec8, 0x88aa866c, 0x53679e79,
+0x1d059636, 0x73deea61, 0xab88d018, 0xf205a6e8,
+0x2713f775, 0x0b1ed394, 0x4059b42d, 0x0213ac4a,
+0x39085cb6, 0x5600cfe8, 0x52093101, 0x649fbd0e,
+0x74c0702a, 0xe7629810, 0xa681aacd, 0x60eaa0a8,
+0x72cc508e, 0x9e1d776c, 0x5e408e10, 0xa838335a,
+0x2fd49374, 0x8b7b2d59, 0x2f316ab4, 0x75a1e5d9,
+0x8f2c0096, 0x79403937, 0x011c00ab, 0x1f2117be,
+0x18b9f030, 0x2c1e9b35, 0x4e637614, 0x1087e918,
+0x6a880f50, 0xdab80288, 0xfb368f0f, 0x81e49f3f,
+0x6d80b329, 0xc8b5bf26, 0x80a78d17, 0xc361dc54,
+0xc2868734, 0x7378c8be, 0xb7e6b6de, 0x1f0d7ea3,
+0x64f0dca1, 0x0b05acfb, 0x1b2558be, 0x7887ea9a,
+0xfd8e6536, 0x60a59aaf, 0x41cbb807, 0xd5aa6d97,
+0xd5f292b9, 0x9d881fc1, 0xa9469e79, 0x86032d6d,
diff --git a/src/cpu/intel/haswell/microcode-M3240660_ffff000b.h b/src/cpu/intel/haswell/microcode-M3240660_ffff000b.h
new file mode 100644
index 0000000000..855b565e5f
--- /dev/null
+++ b/src/cpu/intel/haswell/microcode-M3240660_ffff000b.h
@@ -0,0 +1,1153 @@
+/* 0x40660 built on 07102012 */
+0x00000001, 0xffff000b, 0x07102012, 0x00040660,
+0xa882cff8, 0x00000001, 0x00000032, 0x000047d0,
+0x00004800, 0x00000000, 0x00000000, 0x00000000,
+0x00000000, 0x000000a1, 0x00020001, 0xffff000b,
+0x00000000, 0x000011c1, 0x20120710, 0x000011c1,
+0x00000001, 0x00040660, 0x00000000, 0x00000000,
+0x00000000, 0x00000000, 0x00000000, 0x00000000,
+0x00000000, 0x00000000, 0x00000000, 0x00000000,
+0x00000000, 0x00000000, 0x00000000, 0x00000000,
+0x1ff7ada1, 0xe67ddf49, 0xd16f59fe, 0x3de7b6b8,
+0x977a1339, 0x9b309930, 0x77c11ed6, 0xe1663e0f,
+0xa19308a3, 0x5b19c4b7, 0x4a1b425b, 0x7d6a74f6,
+0x81624193, 0x3a559605, 0x5475280b, 0xe7319d58,
+0x48624ca7, 0x507af030, 0x3b32d96a, 0x30164068,
+0x5284d2f5, 0x725b2915, 0xf63c9280, 0x44b7c142,
+0xe67ca7b3, 0xd6f163e7, 0xcdf51f3c, 0x41d180a1,
+0xcc3931b1, 0xf7a544a9, 0x7f6bf77d, 0xfc45a45f,
+0xf0985836, 0x652d7e2e, 0x0324b1f3, 0x24b9548c,
+0x7bcae7a5, 0xdcdebf79, 0x27015922, 0x0c83c606,
+0x3d2ceeb7, 0x61c5eec8, 0x6b6899c6, 0x3e500531,
+0xf08bfa44, 0xb304a8f4, 0xcee8f713, 0x2912c786,
+0xfae6c34c, 0xa5292960, 0x7d63e389, 0xaa257a01,
+0x1fb25054, 0x963fc676, 0x5bcb9fd3, 0x58f369a4,
+0xf6e3beb2, 0xa58b5eb0, 0x33c7eba4, 0x37fe8b66,
+0x00714403, 0xf0fd0c4e, 0xaa122996, 0x9a55b184,
+0x00201507, 0xc9fb6e3a, 0x11ab60c8, 0x80ff6e84,
+0xc37aabdd, 0x0fc23175, 0xb0b18c34, 0xf1ec806c,
+0x00000011, 0x480b4ccc, 0xdb6de7d6, 0x000cdf71,
+0x1765d536, 0xc4184c2a, 0x685c285b, 0xd2bcb822,
+0xeaf8abc0, 0x34cfc49f, 0x78c34792, 0x28b4da5f,
+0x3d12c965, 0x4c550491, 0x0506a830, 0x4da70368,
+0x5ff5f5b0, 0x1a964986, 0x5809925b, 0xbcfc5f37,
+0xba8b3d35, 0x3ad36e1c, 0x0ccfd073, 0x0e3c3aca,
+0x68c92c72, 0x9c159ac2, 0xfdce3c9f, 0x34bb6e5f,
+0xae6b60cd, 0x2e1f315c, 0xbb18055e, 0x173fe3c5,
+0x81c53bb5, 0x472dcb5d, 0x97cd328c, 0x72a38996,
+0xa5083145, 0xae2387f9, 0x29c7fedb, 0x10e52ad7,
+0xe4177af8, 0x95c54b7d, 0x10876a03, 0xc9d600d7,
+0x897d1cf9, 0x8add358d, 0x6c6cfd85, 0xf95ee134,
+0xf31f1fa1, 0xbad3734c, 0xe9e58304, 0x9f0f99b0,
+0x7103e8cb, 0xc66c6e93, 0xb2df78f3, 0x28081f82,
+0xe161acc1, 0xa9e20494, 0x454c52b5, 0xcaa9fd92,
+0x12aaa198, 0x2d4df98c, 0x3f867734, 0xe0301e6c,
+0x5be1d70c, 0xf8309a0a, 0x6bbf90c3, 0x856a1429,
+0xc5244952, 0x9e036d0e, 0xe85891b4, 0x819d3062,
+0x7658991b, 0x755df5a9, 0x88521603, 0x3639bbd8,
+0xfd51e58a, 0xfbc33e69, 0xcd813bac, 0x0b482ca0,
+0x0c7a5d31, 0xc5612d4e, 0xfcdd6828, 0xdcf2d51c,
+0xe3adf68b, 0xc60a64c0, 0x960f6a4c, 0x207624a4,
+0x604f8610, 0x6d2fc86d, 0xf6fa94c7, 0x68ee2a85,
+0xc0b21534, 0xb72fd50e, 0x5f8f27db, 0x6a8f6883,
+0xcc97c50a, 0x4fe554f1, 0xc6113bb8, 0xc4df7e17,
+0x4b88af55, 0x44267a1b, 0xfcbc5017, 0x4a774e4d,
+0xa8da382a, 0x12243bdc, 0x4642f769, 0xae5c03a8,
+0xcc619a73, 0xd368baf8, 0xa4c1c1c4, 0x0adaafb2,
+0x2e8f5353, 0xd595612b, 0xadff0cfa, 0xa85814f2,
+0x95286967, 0xd948bae9, 0x368a9ba9, 0x79e3326d,
+0xfc5a6965, 0x58f52c5c, 0x63f450bd, 0xf5e8d91b,
+0xd6ce6c2e, 0x2b034b0e, 0xf5f27cc9, 0x279aed70,
+0xe4454322, 0xc341cc3b, 0x58170512, 0x5fd0cece,
+0x1388d7df, 0x05c42e9f, 0x7142e271, 0xfa905cf0,
+0x22c54f35, 0x7186deef, 0xcc0fe959, 0xc9cf2316,
+0x90cd756d, 0x9081469b, 0xbce19677, 0x8fb9df2d,
+0x921f75b4, 0x7e1ece29, 0xd82dd344, 0x197ae9fb,
+0x20008249, 0xf9f9fda6, 0x7f94d730, 0x16357312,
+0x277a1edc, 0x5e8e0e30, 0xa5d91c92, 0xf7d5193d,
+0xb469da53, 0xb6a1f3de, 0x7cee6da8, 0xd8261c52,
+0x884b7eaf, 0xb6137120, 0xa7c12e5b, 0x9500d95f,
+0x75d94d37, 0xcd9b917e, 0xbf1862aa, 0x4922ecec,
+0xc79efc26, 0xf81eda28, 0xf72d9730, 0x11189de8,
+0x5f1cbf69, 0x31d466cb, 0x685da66d, 0x96d1f3f5,
+0x5ac24787, 0xb8d1cdbd, 0xe62145f3, 0xb2cc24b6,
+0x04b041df, 0xbc87a106, 0x7e1a5d29, 0xc76846c1,
+0xbec3cab5, 0xa0b380d5, 0x7e469978, 0x601eee3c,
+0x98987ec0, 0x0d540b0f, 0xf5ced019, 0x620f9512,
+0x652dd7d0, 0x8942e181, 0xf35f6743, 0x6468c26b,
+0xe9d97b6e, 0x25c2c688, 0x64e1bf83, 0x83b0e78d,
+0x82ed883f, 0xeecbe555, 0xb5d077dd, 0x1577b1ae,
+0x06680dd6, 0x641e0ea4, 0x8d1a1f7b, 0x651a54d0,
+0x01d2feef, 0x0a2dec2d, 0x9b64c05e, 0xd9cd30cd,
+0xc540a9e3, 0x32ec977a, 0xfb720742, 0x6d3df6ea,
+0x0a9b6867, 0xaa5be556, 0x63bc6d2c, 0x987e7d4b,
+0x520a2961, 0x7132045a, 0x9f0b0ef9, 0x1319e03d,
+0x96117ec8, 0xc870daba, 0x0d0ad2f7, 0xb9aec9be,
+0x1993aac9, 0x9c68b56f, 0xb9f87058, 0x7d8fa93c,
+0x33338095, 0x8bbfd9b3, 0xbfd27b94, 0x48e0e0e2,
+0x8549fa48, 0x788575d2, 0xace94436, 0x5d5f57e8,
+0x023fa4eb, 0x7bd1e063, 0x270c4228, 0x11e4f41c,
+0x265f6645, 0x718f2c7f, 0x6ebc88d3, 0xd8079739,
+0x0019ccd3, 0x67336012, 0x9dbb89f0, 0xe394618d,
+0x125ea033, 0xeeba68c4, 0xc1c28a0f, 0x2e2a0a4e,
+0x52876a7c, 0x11f32147, 0x27926c85, 0x0ed49218,
+0x1e212ebf, 0x027058d9, 0xca271e42, 0x94923f25,
+0xfb58ca38, 0xff7ea9e9, 0x10ac83af, 0xa913f9aa,
+0x24718089, 0xf7a53cfc, 0xc280b538, 0x81587f94,
+0x422c2628, 0x1605193d, 0xbd383667, 0x0a9e3daf,
+0x3563c712, 0x2adb6961, 0x35c6658e, 0x9d6279b3,
+0x7937ac5d, 0x726ac41d, 0xd927d701, 0x2c81e0da,
+0xd330dcf2, 0xab2bff53, 0xb2611be0, 0xfa887e5c,
+0xd25d012b, 0xb68ab827, 0x6f956859, 0xfe02af8c,
+0x1cb944a3, 0xded6edee, 0x9ea78f4e, 0xa27011c9,
+0xd901e55b, 0x7361dd4d, 0x052707ff, 0x56a2f216,
+0xde9156f5, 0x1849774f, 0xf163a658, 0xee15f902,
+0xae02aac4, 0x445a5fcc, 0xf7ecf535, 0x3dcb4cd5,
+0x7ce9bd26, 0x14d87d9b, 0xd99c988c, 0x875023a4,
+0x72b36509, 0x27bb98b3, 0xb4785c65, 0xea9830fd,
+0x4ca22877, 0x9f7f42e0, 0xfe1b50a4, 0x71c40e18,
+0x28d0348f, 0x1520b97d, 0x09f855c0, 0x5df295b6,
+0xe72e134d, 0x4afa435a, 0x964f7821, 0x8058e28c,
+0x42c7100d, 0x8d6849d9, 0x4268df28, 0x0c93ee17,
+0x80dd73b6, 0x97e95429, 0x2348f8c3, 0x82daf2cc,
+0x5f7e5bad, 0xca96ce96, 0x70e5a8af, 0x2b39329f,
+0x59bb385f, 0xb826195f, 0x50cd51a2, 0x5b851acc,
+0x8892c127, 0x687a8d99, 0xf4731404, 0x69bea0c6,
+0x75b0b75c, 0xb5e4b785, 0xb7c8d2d5, 0x73ba0e9a,
+0x3a311e39, 0x3573befa, 0x62d65719, 0xddacf64b,
+0xd5058b2c, 0x167dcaf9, 0xd1069643, 0x47dc9829,
+0x4044c6f2, 0x05e2e789, 0x7a9491e6, 0x43bb7e0c,
+0x9c7b9648, 0x21aa7168, 0xb0736e68, 0x380a00f3,
+0xda6ffd04, 0xabc05138, 0xb4fcd56c, 0x1f3bcfb1,
+0x8bd59410, 0x01eb9490, 0x66ef8ddc, 0x5c6e72c4,
+0x3e117c9c, 0x61e077dd, 0xea2e96a9, 0xba0936fc,
+0x21064541, 0x24fed220, 0xff02e43a, 0xe7f8810c,
+0xf3872867, 0x7454f13d, 0xc7b610e9, 0x3d73b8cf,
+0x0384cdad, 0x5f7a172d, 0x3b6baaa4, 0x7e677431,
+0x8a0b6362, 0xfd8d7823, 0xd8cabfb6, 0x0fb3d552,
+0xdebecad2, 0x0b07db05, 0xc0d76c20, 0x1aa7db91,
+0x1be9abb1, 0xfa661731, 0x3c8aa273, 0x8e70e00b,
+0x6d8a6a25, 0x7d6f38d5, 0x298370fd, 0x0d932b39,
+0x1d26b69e, 0x1e8dcfc2, 0x70f2825a, 0x613bd515,
+0x74eaa55c, 0x757da6a5, 0x76d06b8a, 0x27e86957,
+0xf67d21b6, 0x69944586, 0x09ea4ba5, 0x4e952542,
+0x0caec887, 0x795fcfdb, 0xcd290b12, 0x0e249485,
+0x6f8a14f9, 0xf7bda988, 0x5b5ef960, 0x0b823488,
+0xd88648d7, 0x20f4d220, 0x6f3baac9, 0xe54cb2aa,
+0xcd542951, 0x748ee3c7, 0x8668853a, 0x95f5fe78,
+0x2ce72653, 0xdcfbbc58, 0x742ad45b, 0x3d2a9a02,
+0x065ad857, 0xbe6cea1b, 0x4d81cafc, 0x258d4b2d,
+0x7d0b5d61, 0xa01c187f, 0xb6e3934b, 0xa8c5f12e,
+0x98eaed95, 0xafbb6f13, 0xa2b5abdb, 0x0fcc93e1,
+0xc2d09e18, 0xf82a6c76, 0xed92c7ea, 0x4225f256,
+0x55395aaf, 0x2d3418ee, 0x39c764fd, 0x3c1f45da,
+0x7ea6df70, 0x9f849b7d, 0xd67b062c, 0x096f0bdc,
+0xa12fc63e, 0x6534750c, 0x640afb20, 0xea691235,
+0x69b6f5e3, 0xc82f750d, 0x648764f1, 0x23c08ebb,
+0x4f61cc48, 0x30dfc6fa, 0x91cca2d1, 0xbf78ff85,
+0xc42a6578, 0x94a52d22, 0xe0e661d3, 0x38f38a2c,
+0xa1247441, 0xcc629f49, 0xae77f81d, 0xd9ae5b0a,
+0xc96df3f2, 0xefdc25be, 0xd20aa371, 0x951acefc,
+0xb5c4892d, 0xb48135db, 0x301de6c6, 0x157aa4b5,
+0x72c543f3, 0x1b63e2eb, 0xd038986f, 0x80dce4ef,
+0xb4624378, 0x1619febf, 0x782ee04b, 0x9a7235d9,
+0x89569035, 0xd853958b, 0x8f6a6a4c, 0x6da02ec7,
+0xf555a674, 0x03fd0eb7, 0xd388f391, 0x228f9060,
+0x084c972d, 0xc5676f44, 0x84995e38, 0x018daa8c,
+0xfc22788c, 0x7c6bd63a, 0x8bda5eaa, 0x2b2923f7,
+0x59a97616, 0xf8d38ce5, 0x4651996e, 0x0b87bdee,
+0x0bf6153d, 0x9891d21c, 0xe99a1295, 0xf145cfe2,
+0xfa2dc566, 0x05ec6c2b, 0x26b29f42, 0x66e119f3,
+0x7b4f675f, 0xf7eeefba, 0xb2d1650e, 0xadcde98c,
+0x12f732bf, 0xae96a355, 0xb1f8fc9a, 0x5ca9700c,
+0xca806581, 0x9b14027d, 0xac0ddec8, 0x42371805,
+0x6f4e445c, 0x5c999326, 0xdad40547, 0x3725ed58,
+0x1c9b9135, 0x6c6d6288, 0x0f3143e0, 0x30c0bbdb,
+0x159c9447, 0x17a7db00, 0xb7ed03e7, 0x538673e4,
+0x6668c637, 0x1c5e4ca5, 0x223d6250, 0x338359ea,
+0x0d458bee, 0xe2886c6c, 0x87f83ee2, 0x8eff181a,
+0xbeaeb6ab, 0x40294569, 0x7b6a813e, 0x2594d208,
+0xc4bd77eb, 0x4cf2cead, 0x747fa78a, 0xab289d1c,
+0x84c7f602, 0x1671a29c, 0xc1717572, 0xd1d946de,
+0x80d67719, 0x540604b4, 0x07ea3468, 0x914ca5a4,
+0x2ff43018, 0x0c80589d, 0xd7f47a0d, 0x3352a600,
+0x45425f2d, 0xcfe236ce, 0x4e1715ab, 0x1a3610fd,
+0xe850ed81, 0x853dbfb0, 0x1703a45c, 0xdf419c55,
+0x749c3658, 0xce26c629, 0x6bc2d78f, 0xc2bb4dba,
+0xbcec7f66, 0x4296d407, 0x99d16376, 0xad1a1137,
+0xc5a83a85, 0x7444ec0d, 0xc8bf4c01, 0x54c43ed5,
+0x32f9823b, 0x842c9295, 0xa1d8007b, 0x80fa6d42,
+0x9bf009b6, 0x5290644c, 0x9a24c075, 0x58f4ca7a,
+0x9b699e44, 0x985c751a, 0xbcf9c22e, 0x29dc0d6f,
+0x00dc1b8d, 0x643cd9bb, 0x959bdfe1, 0x58dd1c9c,
+0x5a4d2b3d, 0x8742f2c7, 0xa03abf55, 0x24403210,
+0x6d0d1d5c, 0x45ba1c4d, 0x23117eaf, 0x144a4ea2,
+0xbdae7f64, 0x2ad0a8fe, 0x9fa12271, 0x08d31b7c,
+0xe7c17533, 0x646726ff, 0x2fff165d, 0xd76895d5,
+0xcc23399b, 0x40a4b16b, 0x14135e83, 0x3ac1ac81,
+0x8a470059, 0xe5af8f50, 0x4906108a, 0x9fb71659,
+0x8634549b, 0xf1edfaeb, 0x6a31016b, 0x1fab821f,
+0x290b458b, 0xdf17edc8, 0xa13ad6d1, 0x925e2a12,
+0x8e3691ff, 0x95ed2c48, 0x74e7fea3, 0x97d50485,
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+0x320098aa, 0x9f7786f2, 0xec50f262, 0x7902faa4,
+0x051db255, 0x4d7f4dfe, 0xb1539d59, 0x5541d770,
+0xc4ff1118, 0xd4094d58, 0xda9416c1, 0xf8349318,
+0x855a7d61, 0xf491eda7, 0xd5a8d841, 0xa787e9c6,
+0x7f2bd161, 0x442a0aef, 0x738287ae, 0xb60aa175,
+0x07c65ff8, 0x6b9f8ca2, 0x314ea5cd, 0xf777daad,
+0x308b17b2, 0x81cf18ff, 0x371267e4, 0x5d3c2b3c,
+0x83ba613c, 0x9632db28, 0xd399ade1, 0xf7e83f7f,
+0x5488c51c, 0x86c70fad, 0xe479bd12, 0xb219ff0a,
+0xf3f13ee3, 0xa9de0f7b, 0xe834a5c0, 0x1af639c4,
+0x1ee50626, 0xa982dd5b, 0x6fca001b, 0x7f9db2c9,
+0x25b87ff2, 0x2b72ce75, 0x443afb46, 0x641df6a0,
+0xa00dfd94, 0x85e9c294, 0xdbc78f86, 0x25cdcaa0,
diff --git a/src/cpu/intel/haswell/microcode-M7240650_ffff0007.h b/src/cpu/intel/haswell/microcode-M7240650_ffff0007.h
new file mode 100644
index 0000000000..b1157d60c7
--- /dev/null
+++ b/src/cpu/intel/haswell/microcode-M7240650_ffff0007.h
@@ -0,0 +1,897 @@
+/* 0x40650 built on 08132012 */
+0x00000001, 0xffff0007, 0x08132012, 0x00040650,
+0xbaeb63c8, 0x00000001, 0x00000072, 0x000037d0,
+0x00003800, 0x00000000, 0x00000000, 0x00000000,
+0x00000000, 0x000000a1, 0x00020001, 0xffff0007,
+0x00000000, 0x00000dd1, 0x20120813, 0x00000dd1,
+0x00000001, 0x00040650, 0x00000000, 0x00000000,
+0x00000000, 0x00000000, 0x00000000, 0x00000000,
+0x00000000, 0x00000000, 0x00000000, 0x00000000,
+0x00000000, 0x00000000, 0x00000000, 0x00000000,
+0xde429059, 0x5e47e5f9, 0x4178c7e5, 0xc173f907,
+0x7d1b18cc, 0x14d707f5, 0x7cd90b57, 0xb13efbdb,
+0xa19308a3, 0x5b19c4b7, 0x4a1b425b, 0x7d6a74f6,
+0x81624193, 0x3a559605, 0x5475280b, 0xe7319d58,
+0x48624ca7, 0x507af030, 0x3b32d96a, 0x30164068,
+0x5284d2f5, 0x725b2915, 0xf63c9280, 0x44b7c142,
+0xe67ca7b3, 0xd6f163e7, 0xcdf51f3c, 0x41d180a1,
+0xcc3931b1, 0xf7a544a9, 0x7f6bf77d, 0xfc45a45f,
+0xf0985836, 0x652d7e2e, 0x0324b1f3, 0x24b9548c,
+0x7bcae7a5, 0xdcdebf79, 0x27015922, 0x0c83c606,
+0x3d2ceeb7, 0x61c5eec8, 0x6b6899c6, 0x3e500531,
+0xf08bfa44, 0xb304a8f4, 0xcee8f713, 0x2912c786,
+0xfae6c34c, 0xa5292960, 0x7d63e389, 0xaa257a01,
+0x1fb25054, 0x963fc676, 0x5bcb9fd3, 0x58f369a4,
+0xf6e3beb2, 0xa58b5eb0, 0x33c7eba4, 0x37fe8b66,
+0x00714403, 0xf0fd0c4e, 0xaa122996, 0x9a55b184,
+0x00201507, 0xc9fb6e3a, 0x11ab60c8, 0x80ff6e84,
+0xc37aabdd, 0x0fc23175, 0xb0b18c34, 0xf1ec806c,
+0x00000011, 0xa5f6213d, 0x4c3e7f1f, 0x13a90e88,
+0x47b7d6ec, 0xf571bf23, 0x50ddfe65, 0x479fdaf5,
+0xcd75485d, 0xbe558d1d, 0x2df5284a, 0x4c97c566,
+0x154ba1be, 0xf77aa9e8, 0xc9ca22cd, 0xb83e0b19,
+0x7f2153d7, 0x552930e0, 0xf4477e59, 0x75eec500,
+0x8d9c0b08, 0xe1c173bb, 0x33569053, 0xff2f1473,
+0x71de2e2f, 0xa8f86c8c, 0xde68ce7d, 0x7d2940d6,
+0xcfe8c5f0, 0x978e28e8, 0xd23ab801, 0x4acfc2c7,
+0xeeaa8b75, 0xf4817f5a, 0xea1664b4, 0x76374ace,
+0x3c50dd90, 0x7368b116, 0xd0a10979, 0x428f0221,
+0x18ba6453, 0xfafec8b7, 0xb48db289, 0x506e23d6,
+0xaabeea21, 0x0c9289a6, 0x14aee813, 0x4a1e6f14,
+0xdc2f70b9, 0x7f579faa, 0x1639a925, 0x2afd96e9,
+0x38c5bf51, 0x832e7063, 0x973d9697, 0x5fe400f5,
+0x46032c71, 0x9e335517, 0x12ee90f6, 0x3b3391ea,
+0xdc9cdfe7, 0x804a36f5, 0x5e271bd8, 0x756af6d9,
+0x0a17677f, 0x134ebb47, 0xcfc9965d, 0x2594bc24,
+0xaa26ea5a, 0xb8ab648e, 0xfa47d751, 0x1ab2e541,
+0x536be73e, 0x5e0dff9a, 0xdf0e8762, 0xf1ea6de0,
+0x718e58c2, 0x4e566bb8, 0xafe8103f, 0x1bc8fd5d,
+0x4a035c53, 0xacba0dc7, 0x45bd0e74, 0xa9b82f72,
+0xc52ff600, 0xb8f3ed00, 0x83901bc8, 0xc724165f,
+0x37be294c, 0x21458e90, 0xe9e06f27, 0x428aa4ed,
+0xdbe671d7, 0xc9e4da8e, 0xa1d035b5, 0xab3cd5f1,
+0x321fb426, 0x1504431d, 0x21ce98bb, 0xc36472ca,
+0xe48c143b, 0xed0d0dd1, 0x8e902cd1, 0xc8b08e45,
+0x438949de, 0xf9cad1f0, 0x85f2e250, 0xf435da99,
+0x0227bd81, 0x6b02307a, 0xb2a6167f, 0xe9897016,
+0x58c9c43d, 0x58b458e2, 0xadc5d080, 0x3d699203,
+0x4742176d, 0xef29c1ab, 0x52a0f932, 0x3e1b23af,
+0xab6a31d6, 0xab9ced6d, 0x61340822, 0xc33ba5bc,
+0x1bc40c4d, 0xab33fa59, 0xd08d9ddc, 0x484049bf,
+0x7a572f4e, 0x3225d01b, 0xaceda13d, 0x1ec90bc3,
+0x9f402965, 0x4894c12a, 0x72a120e9, 0x7aadb73f,
+0xcba5e444, 0x88d94908, 0x57e241e7, 0xead7fa13,
+0x9257d68f, 0x816fd674, 0x1820fa2c, 0xc31e4d24,
+0xfe1d36c3, 0xd65dda50, 0xd31fd7ee, 0xb9ca8e69,
+0xd3e04c42, 0x6b8bb35c, 0x874c68e0, 0x08e4e24c,
+0x612586d4, 0x417952cc, 0xc6351b8a, 0x8682cfbf,
+0x5418993b, 0xc85089d9, 0x3e547bad, 0xc904a3ed,
+0x679e3bf1, 0xc5e8cf6b, 0x4370a103, 0xba4dab8a,
+0x25d0ae4a, 0x79a5cae0, 0x1ade6919, 0x3c915dbb,
+0xb1d56d12, 0x94c186d5, 0x6d68313a, 0x0abf1aaf,
+0xa937dd41, 0x9eafe75b, 0x54c831d8, 0xcb69c354,
+0x3bf4f413, 0xa408f4ad, 0xe669d950, 0xebae6c75,
+0x58d289e4, 0x932ed8ac, 0x24fbb89f, 0x09b85d96,
+0x0488f4c4, 0x23e706f9, 0xa509821f, 0xc4f728e4,
+0x10159886, 0x8ad9abb2, 0x8d60b096, 0x104f9407,
+0x0563e5fa, 0x9f2a185c, 0x6b0d5ee9, 0x917f0833,
+0x132f62b0, 0x9c9de1af, 0xfb35fecb, 0xa2955743,
+0x13556f40, 0x3088c822, 0x2308e4f4, 0x5ea61fed,
+0x50cadcf5, 0x0d3fc6f8, 0xd3ec64a6, 0xf31b9b87,
+0xc5c15f6f, 0xc28dcdb5, 0xe7ee3298, 0x16059909,
+0x8e4137e4, 0xbdd66612, 0xc3e1c984, 0x19b02c18,
+0xdf3f56aa, 0xb59509dd, 0x23c0c479, 0xbbcce51c,
+0x7817299c, 0x38fa17e0, 0xc065556a, 0x8c7fcce3,
+0xf5974dd7, 0xc46f375c, 0x4843d245, 0x766d6bc1,
+0xc6a6c95f, 0xeeb43f14, 0xba692967, 0x03d65aef,
+0x48d40627, 0x8b5207f6, 0x209a3620, 0x0534affd,
+0x73675d8f, 0x6e7da0b3, 0x683dbbd9, 0x258ff122,
+0x76fec635, 0x38adb43e, 0x13865990, 0xc63f0be3,
+0x8e0faf6c, 0xf4c9bc52, 0x8ba3eec1, 0xbb83ae51,
+0x0bcfe7ff, 0x6b0c87e9, 0x62fd054d, 0x58ec7fb7,
+0x7ee720af, 0xbe752edc, 0x34a6b393, 0x900beaff,
+0x129bca50, 0xf138ec56, 0x19a9c071, 0x509da2e8,
+0xb1e93845, 0xa9fada7c, 0xb1ac79c4, 0x89f43cab,
+0x41a6ce12, 0xa41e3592, 0xca1a315b, 0xe48953fb,
+0x020f5a5b, 0x8429118b, 0xc541b1e5, 0x74699f42,
+0x6fb8ba4d, 0xe3bbba41, 0x5978a354, 0x6a0cb98a,
+0x1cda611e, 0x712b4dbd, 0xa509df61, 0x170d7f17,
+0x4ebc3033, 0xac2fad83, 0x35b30875, 0x373b9ba6,
+0xed269abc, 0xed6c6f2d, 0x33d374c3, 0xe270b1d4,
+0x98fa18d6, 0x3729a2f8, 0x45d47a16, 0x218ada10,
+0x4f3fd842, 0x07b06600, 0x861e257a, 0xbe14066a,
+0x2bed0580, 0x6f862fff, 0x4c40cee8, 0x247b9501,
+0xfa49656d, 0x32671541, 0x92b1468b, 0x5910423b,
+0xb8fa9dc4, 0x2f97339a, 0x1d32034d, 0x569ea757,
+0xbbc3a3a7, 0xecb1803a, 0xddbea4d7, 0xde2e65c0,
+0x3e3b9cdb, 0x79d50365, 0x445bec79, 0x6d6e9525,
+0xdd6cac48, 0x94ec33f0, 0x5c78943d, 0xb87565f2,
+0xd149928a, 0xad39bbd8, 0x8a49aaf1, 0x8c503427,
+0xb699c8ec, 0xfbef7198, 0xcae17d67, 0x415c8594,
+0x089c2f7e, 0xe2b4a22d, 0x17788281, 0x506c50a6,
+0xe65e6ff4, 0x0f007e17, 0x3d611dd5, 0xdbdf436b,
+0x6224ff7c, 0xfd37b4a1, 0x20fdca9b, 0x93bbe39f,
+0x05b6625d, 0x27392f71, 0xc1b29aa5, 0x5af4fc64,
+0x98b39b82, 0xfaa95459, 0xd746ece5, 0x07edfe4b,
+0x8d376fff, 0x6b6f2676, 0xb8606790, 0x2d97d392,
+0x2e2c0cab, 0x8b5e19c6, 0x4e201e48, 0xfffc0942,
+0x1623e57e, 0x364f160b, 0x231732b0, 0xbc35e1d2,
+0x7a9bac6a, 0x87682488, 0x863ba638, 0x89507dc0,
+0x5df119bb, 0x84aededa, 0x38d0bde4, 0x30447148,
+0xde21bfb1, 0x637fd2ed, 0x504950d8, 0x28a11edf,
+0x601022d2, 0xd5055454, 0x7aa6f597, 0x45076dba,
+0xb4144de7, 0x071c3c3f, 0x3ec7dfc2, 0x94dda8ff,
+0xcbf010ac, 0xf1756cc9, 0xa1cdf230, 0xd5dcdad0,
+0x7b389ccf, 0x5aeca312, 0xea12b3f3, 0x4df41c14,
+0xa7a62abe, 0x664aca2b, 0x77c44afc, 0x582360c3,
+0x18068ac3, 0x57a8b000, 0xf3d97ae3, 0x65026c78,
+0x323bc374, 0xdcc6c805, 0x3132fc2e, 0x3a5fc067,
+0x811ae1af, 0xac3eaf2f, 0x906a5019, 0x5d68cd4e,
+0xa99f3669, 0x585b5912, 0x3e8f438e, 0xe09a385a,
+0x327d27f2, 0xa1f57a36, 0x439b5798, 0xddb57964,
+0x9c49c90d, 0xdfb51ced, 0x373d5771, 0xb06368e7,
+0x4023e0d8, 0x96541876, 0x00812d9d, 0x9453b8ea,
+0x8edce7f8, 0x5f6a3153, 0x6e326bf6, 0x12bdbc11,
+0xf6a3ff4a, 0xf9e9895a, 0xf337cb7e, 0x55f63f3f,
+0xb286f188, 0x8e66d63d, 0x0c677aae, 0x1ce018bb,
+0x794f4210, 0x771ee72b, 0x5230d96a, 0xa61e6308,
+0x98c1b0d1, 0xb946302c, 0xbf061220, 0xd906821c,
+0xddde4d5e, 0xf0a365d8, 0xe48b38cc, 0x070521e7,
+0xa95e1bbf, 0x6960834e, 0x458ff508, 0xae06010f,
+0x5bfc3a8c, 0x543464be, 0xd0aa32e0, 0x8e56415d,
+0x91ec7ca0, 0x9a45b1e4, 0xf3d4efc3, 0x12f469ae,
+0x26a186d8, 0xeafee135, 0xef773153, 0xb8aed6f1,
+0x1b8673dc, 0xd797accd, 0x3e53a7f0, 0x22b11fe1,
+0x7527e0fe, 0xfa19cc41, 0x8ab0d9a2, 0x8e35bf24,
+0x7858c291, 0xe792110c, 0x14108460, 0x96bf4ef2,
+0xd45a928e, 0x7ea7c1fa, 0x75ba21c0, 0x7f989da0,
+0xc8065224, 0x949a5efd, 0x36f956c5, 0x08507305,
+0xf5e33b5a, 0xcf1ef444, 0x9792b9d1, 0x9352e48d,
+0xeaf81317, 0xb787a480, 0x2d4b8f78, 0xc3336174,
+0x37940cf0, 0x19e0969c, 0x951cdcbd, 0x5ac58c49,
+0x75835178, 0x09b9aa85, 0xfff9fe36, 0x8ccdf3de,
+0xf7961b8d, 0x3b3c0b54, 0xfdaca8b0, 0xfaf7412a,
+0x6af0d993, 0xe52b2d6f, 0xe7020726, 0xca2182a5,
+0xa99d1628, 0xd98c538a, 0x209c0503, 0x0f6a9e33,
+0xa84394e7, 0x509962ee, 0x9c3b3003, 0x4e9ac79c,
+0x8be469e1, 0x64111a88, 0x265d7b21, 0xde93f751,
+0x4e2050a4, 0xa7d79c08, 0xeccd6553, 0x75619d71,
+0xfe982494, 0x4fa2f243, 0x166f7015, 0x7db76a2c,
+0x0832a935, 0xbd967ff7, 0xa908724a, 0x392fbeaa,
+0x64108b97, 0x0539c65e, 0x3b6f26a2, 0x92eb0d48,
+0x720914cd, 0x4ca6486e, 0xb274acd7, 0xfe19bd38,
+0xa40ae91f, 0x2aba2b01, 0xdf2fada7, 0x5960bba7,
+0x06473cf5, 0x55a3a150, 0x06fb5eb7, 0x72901380,
+0xf868eab5, 0xf9324b56, 0x0df3d887, 0xcd94a107,
+0x773b7545, 0x3675fb0e, 0xba884359, 0xbfe0250e,
+0x8ddc125e, 0x1f177467, 0x73fd4a4c, 0x3bb2d4ea,
+0x9101fc78, 0x35477604, 0x61141387, 0x79e44cb4,
+0x0272093d, 0x45e916f4, 0x9d06f5f6, 0x20682b26,
+0x60f877b4, 0xc3fa25cf, 0x9db61d8d, 0x1b49af8a,
+0xd623c4ed, 0x55623ff0, 0x6ef4d78e, 0xe482ddc0,
+0xd3500f1f, 0xfa7ed79d, 0x9aed7258, 0x6f856c74,
+0xfa4c7b62, 0x15f7c113, 0x8948fe2a, 0x40c4745b,
+0x38ef9301, 0xe9a0d7db, 0x38abc988, 0xee8e94f9,
+0x6df8453c, 0x2f095383, 0x9c102a51, 0xb1faa962,
+0x7f09fd6d, 0x3ae0a020, 0xa7a30c8c, 0x28c58339,
+0x6550ae39, 0xd65ce5f2, 0x7f618152, 0x32d91963,
+0xb694b890, 0xc7d54821, 0xc4a32cea, 0xbcf6df28,
+0x0e84e7b6, 0x80d37757, 0xa87d4a39, 0x2a136845,
+0x6b4fc380, 0x534fe27d, 0x79b69696, 0xdbffccc0,
+0xb32e908a, 0xc87e4e4b, 0x325c2d76, 0x4e18cc11,
+0x3daed957, 0xd568461d, 0xf605d1be, 0xeb96b221,
+0xdc8efe67, 0x35039b61, 0x92d9e355, 0x6b6c6e96,
+0x1eeb4a41, 0x0bed14ce, 0x4107eed0, 0xc4dd9c9f,
+0x72b1bf6c, 0xfea4c4aa, 0xc02b4421, 0x63a41c17,
+0x4abaaab6, 0xb4808bc2, 0xd3b5e7e0, 0xd5bfa9c9,
+0x66f141b7, 0x5f84191f, 0x1f67c563, 0xa30ec409,
+0xf506b5c8, 0xbda560e2, 0xf2b94ce1, 0x85211dc3,
+0x54b1cc32, 0x6657ada1, 0xff0c3ee0, 0x5c0746ea,
+0x33bc2add, 0xc39a7f7e, 0xd985aab2, 0x9a433594,
+0x8973cb53, 0xc21a12f8, 0x63ab735e, 0x15a535d7,
+0xf664efdf, 0xb5c30af2, 0x9b076c42, 0x72cc8ed5,
+0x2d9c35f2, 0xfcc2dfeb, 0x98686cad, 0x5a072110,
+0xdadd31c5, 0xe4bbff27, 0x6471c3e7, 0xbb98bedd,
+0x61787352, 0x47f104db, 0x92acbe47, 0xddeaca48,
+0xb1baa422, 0xd2003f0c, 0x934c8332, 0xa13bd139,
+0x0a53f050, 0x28b9e29a, 0xf2805626, 0xff72ceca,
+0x2a9fff32, 0x64a1c61d, 0x15b46d88, 0x7d691a3a,
+0x207eab86, 0xc6135eff, 0x75492f20, 0xd3b52545,
+0x0c2e9fe8, 0x5485d9ef, 0x1e8ab4be, 0x27d05867,
+0x131c267c, 0xe8cd4671, 0x401948f4, 0x5b0828ba,
+0x4ccc4bba, 0x4b4700c6, 0xcf3b8644, 0x9a918fbf,
+0xdb98e32d, 0x97596448, 0x0099a549, 0xce39add0,
+0x75389738, 0xf3bcd5d8, 0x248d5d98, 0x303e6e02,
+0x67babb7a, 0xe56329f1, 0xdf357cdc, 0xbdb7d37c,
+0x12b7e3f6, 0x93e53741, 0xe5cc9521, 0x6babe88c,
+0x91ad446a, 0xf18086cc, 0x07f8e7ac, 0x50ecd2a6,
+0x99e61646, 0x4d4e38c6, 0x261c631c, 0x2c400ebb,
+0x30557dac, 0x39d4f0be, 0x382ef33b, 0x24a6ebba,
+0x2598dd33, 0x6e845989, 0x048e7903, 0x54a89db7,
+0xd9f152cf, 0x36ca3c0e, 0xac795a57, 0x54f2f4e5,
+0x84c0c8a9, 0x383fc1c5, 0x854dc524, 0x38f965c4,
+0xaf0e677d, 0x1815b8ca, 0x3453f1a6, 0x8b64b707,
+0x01c98d2f, 0x96c23c92, 0x869e3c9b, 0x1143a985,
+0xc842d306, 0xada14f62, 0xce22a7ec, 0xbc33513a,
+0x5d0d789c, 0xe7937c9e, 0x447b7527, 0xba9ba3c8,
+0x3352712b, 0x8ff63bae, 0xdc56f11e, 0x5e2496c1,
+0xd92fa227, 0xb8c69ba0, 0x74433f43, 0x2cfeab35,
+0xe49b3e9e, 0xc544b469, 0xaf18996f, 0x026908ca,
+0x60344cc4, 0x73e4b024, 0x73437e57, 0x7132f5e1,
+0x5724337f, 0x677506e6, 0x0950399d, 0x4ece3b52,
+0x32add7e1, 0x055d8162, 0xa39f67e6, 0x3348899f,
+0x7278f636, 0x675ffd16, 0x9d2d33b8, 0x5d9c515f,
+0x19daf00e, 0xcf66b1ff, 0x30f1727a, 0xc7df633a,
+0x83eba3a8, 0x8910fc86, 0xc6d76ba4, 0x826041a6,
+0xda6b8432, 0x51ffaf2b, 0xc07d915c, 0xb6f95bc0,
+0x9cdbb6d6, 0x8e6ebeab, 0x333ff03d, 0x79f2c99d,
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+0xce2b9e3b, 0x5bc8e2fc, 0xf26a32c8, 0x698c9ae4,
+0x864d9d6d, 0x960894e1, 0x33e07c43, 0x98314169,
+0x04f39233, 0x158d72cc, 0x1d139d93, 0x0c714623,
+0xc57fa08f, 0xdac380d6, 0xcb0ab156, 0x72e0bfc4,
+0x8a475c4a, 0x17210b91, 0xdb23bab9, 0xf43fef3f,
+0x4b8f0e27, 0x14f5e8e2, 0x332141f3, 0xca55692c,
+0x4aa0a4d6, 0xbfe77269, 0xf2e29b1c, 0xb19a4a9c,
+0xd038369d, 0xabfede96, 0x97b9c5c9, 0x02a9d7fc,
+0xa22d55ae, 0x27ac7a0f, 0x9d6413ec, 0x93c1b264,
+0xf494a81e, 0x9c5aeda1, 0x1f105e88, 0x0a70ab8d,
+0x13b030d9, 0x3b823dc7, 0x6b2c7321, 0xab690df7,
+0x5f8ceb18, 0x17aaf6d1, 0x19f4c149, 0xfdf4944b,
+0xf75b1f98, 0x7a32d1b1, 0x4b8c630b, 0x235d2e49,
+0x3288c818, 0x27060736, 0x1be821c8, 0x19484ae3,
+0x4d9f0c10, 0x848a6608, 0x3cd837ec, 0x500e1b84,
+0xb10df9bb, 0x0ffa6102, 0x3e1ced10, 0x547c808d,
+0xd4b8f680, 0x0338e62d, 0x2cf62440, 0xe2039f98,
+0xb683f06b, 0x447e034f, 0x6a4a9be7, 0x12800b62,
+0x4dbb8610, 0x960c5f26, 0xcc3cdf67, 0xeac8aa44,
+0x29147e44, 0xe52489fa, 0x154266b7, 0xdd16d7e2,
+0xf5293238, 0x2ec7f232, 0x41f55f3b, 0x08b6dd7d,
+0xd5a519e1, 0x9c2d6ac7, 0xbd38dc40, 0xbbf773e1,
+0x6c44c8ad, 0x4909704e, 0xcf9c835e, 0xac9f0cf6,
+0x02e74db5, 0xa7f9f2f4, 0x9bf17e81, 0xbdd5a357,
+0xe4632011, 0xfae2b887, 0x8e671441, 0x28e62ec7,
+0xf0600919, 0xc7e8dcbc, 0x84aeb74d, 0x8ad38661,
+0x58f15269, 0x1d608461, 0xeddb3ffb, 0x0fe66af5,
+0x7b07ddbf, 0xa662ff0f, 0x68dcc083, 0x848d3fbb,
+0x99af2ee7, 0x2ddb0548, 0xc493b0aa, 0xf9940ee8,
+0x20a5d4db, 0x8ed57bf5, 0x435948ab, 0x97f583e9,
+0xdd5dcd4e, 0x30ccecad, 0xdcc95881, 0x23bcfe47,
+0xe541ab84, 0xf20d9e5a, 0x670521c8, 0x1546cef5,
+0xf29b9947, 0x26c713ec, 0x0deec8c9, 0xc9f7e5bd,
+0x9f519c48, 0x5782ad14, 0xec347973, 0x1bd165ea,
+0x3f54767d, 0x8db25803, 0x3f1847c1, 0x46c1c17c,
+0xae825459, 0x77a00d3e, 0x3838565c, 0x52ca36c4,
+0xe956fb60, 0x80b2c01b, 0xdd0f77cb, 0x825b118e,
+0xae4bf433, 0x716cda7b, 0x6d69e7f6, 0xc016524c,
+0x9a5bb9c4, 0x88720186, 0x5aec39f4, 0x2929f0b6,
+0xb4caf654, 0x445b25f2, 0x215c25d3, 0x16137904,
+0xfb8b7dcc, 0xf11ddde5, 0x9a6cd8dd, 0xbffd8ae5,
+0x6e82a727, 0x3c7b679f, 0x97eaa37c, 0x2693a0fd,
+0xb258524e, 0xbc28c52d, 0x13d1915b, 0x37e62bb3,
+0xa2421c6d, 0x6eeca6cd, 0xa4c61052, 0x1c0681af,
+0xa002f7f4, 0x7e1af034, 0x9870400d, 0xa7aeacdc,
+0xdc93b83c, 0x0ea7c1a8, 0xb0b2d5f8, 0x987b2d64,
+0x8029bbfa, 0x6dd494cb, 0x5adf2f0e, 0x19f05959,
+0x848f6720, 0x85895c26, 0xab1e58b0, 0x520aecd3,
+0x53968185, 0x6db5372b, 0xb0c7081c, 0x73f3068e,
+0xb69ff767, 0xa1599bd8, 0xd840b629, 0x9e05d61a,
+0x98afddcf, 0x2f5c9908, 0xfbb8dab7, 0x7fda7b18,
+0xa07c07a1, 0x275bfd1f, 0xf1a8e940, 0xd0e1efa0,
+0x1588f564, 0xae172c90, 0x3cf19e63, 0xf66ac7ac,
+0x1a082983, 0xeb29faa7, 0xe3ce0951, 0x01a1b56a,
+0xb2901c78, 0xb27e27fd, 0x4fd52832, 0x4188d745,
+0xe925318d, 0x6ebc66c0, 0x0c0c1573, 0x7d26cd04,
+0xbb095fef, 0x1ed71a2c, 0xa6931049, 0x71e91145,
+0xc7601147, 0xa19e02ab, 0x95fa4702, 0xfac784d3,
+0x6ac76420, 0xe8e1e30f, 0x848a7f96, 0xe5ac2116,
+0x624f0147, 0xea992fbe, 0x0b750c31, 0x0e3c210e,
+0x8a73688e, 0xa396aa9e, 0x8eece177, 0x649883f8,
+0x843b98cd, 0x50fe4476, 0x3dcb97f4, 0x54cbee59,
+0x7fa93dc8, 0x54338c09, 0xf5036e89, 0xc6fbe6d3,
+0x659b8de0, 0xa5ea7df3, 0x83d01cc3, 0x83276f3b,
+0x93c09401, 0xa83f8874, 0x44c29328, 0x48260c03,
+0x5f315d0c, 0x7899debd, 0xaaa5b400, 0xc39ae3c2,
+0x1e072918, 0xcf53f8ce, 0xcd7a257e, 0x2d70b59c,
+0x8a41fa13, 0xfccb706b, 0x214aab96, 0xb675e33b,
+0x769eb58d, 0x4fec7b6f, 0xfd880d51, 0xb10e6a07,
+0x0cec1401, 0x81bda3af, 0xe6314ee9, 0xdf7dd5ab,
+0x690e88e5, 0xc64f7835, 0xe0d4b3d7, 0xdd9af7ba,
+0x51dccee8, 0x21cc8429, 0x0602ace7, 0xbb611627,
+0xd80cd042, 0x8ce42d08, 0x9bff2200, 0xca318a07,
+0xbec576c1, 0xaeed80b9, 0x131a7a07, 0xec17fd04,
+0x9a8c78d1, 0x130a0e10, 0xb7c19b6f, 0xfb285ad2,
+0xe901a213, 0x242bd250, 0xee2910d0, 0xd482528d,
+0x0f8c198b, 0x53233b3b, 0xacd3a847, 0x4ed9bd76,
+0xdfff18c7, 0xf3ea0160, 0xd259fe1c, 0x1206c799,
+0xc202fb96, 0xd3afe4fb, 0xa65aefe3, 0xd6cbe7ba,
+0x3c902f88, 0xa2e9e272, 0x0668ec72, 0xd43ccf92,
+0x162fe3e5, 0x110a128e, 0x9e8ce5e6, 0x3602702d,
+0x3367e096, 0x5b6929ba, 0x4aa22359, 0x6a9c5cec,
+0xa0e37b04, 0x98449956, 0xc334045d, 0x86ba286e,
+0x9ff57b22, 0x475c91f2, 0x77bb0b35, 0xea00d5a1,
+0x225126b2, 0x6f40458c, 0x6a8e803f, 0x68536c58,
+0xc7f132b9, 0x384cbd95, 0x397b85dc, 0xd0c0c04f,
+0xa7676ee8, 0xef1f4b17, 0x97cbcd0d, 0x000d34a9,
+0x821bf9cd, 0xbfcd1dcf, 0x75769ad7, 0xe5a07180,
+0x6ebaeac8, 0xf98b5734, 0xa7e21853, 0x6b0adbcf,
+0x7ce7227d, 0xdbfb4e26, 0x7258b1d4, 0x33485f8f,
+0x39c3f013, 0xf3a75342, 0xca99f689, 0xdac1a6b1,
+0x060d7a22, 0x8dec26b4, 0x7340e3c8, 0xb6efbaa8,
+0xabed9bb3, 0x565200ff, 0x46cb2b57, 0xabea0635,
+0x6d3a9072, 0x8f036549, 0x0e0ca034, 0x0936d4eb,
+0xbf26ab33, 0x95630b18, 0x43d7add1, 0xcbcb6047,
+0xdf21f1b2, 0x0dc8bd6f, 0x9ab49f62, 0xeb0505cc,
+0x3abe8b84, 0xb0952016, 0x39dd57dd, 0x6fc0d392,
+0x5c0f9218, 0x0bda02b3, 0xdc6b4d4b, 0x6c843ff1,
+0xabc628d8, 0x6c82823f, 0xf324370d, 0x3fae5261,
+0x9c3988e5, 0x82227173, 0x5631e8a3, 0x8ffe2941,
+0x0a9d8e07, 0x35cec1ad, 0x2086a0c0, 0xb67b505a,
+0x6607a079, 0x4829e991, 0x5e7622f3, 0x87018e34,
+0x8184dd45, 0x6694f40c, 0x9129f8af, 0xc1150659,
+0xc845ad79, 0x0dbe10f8, 0xe3c01bfc, 0x4727e946,
+0x9007f7d7, 0xe858cabb, 0x0a77f5ae, 0xed94e1db,
+0x29f62b6e, 0xae17cad6, 0x5e95456b, 0xb8ff6d0e,
+0xb1fe6f18, 0x221b734d, 0x4168d5f7, 0x926aeaa7,
+0xebfed78e, 0x8130ef84, 0x196586e9, 0xa419723d,
+0x5ac0aadf, 0xe2dc8fa1, 0xa962fc99, 0xde71a0a0,
+0x0e16c3b1, 0x9b0b8305, 0x53cc3587, 0xb48cac6d,
+0xd230a47f, 0xc052bf9b, 0x8c8a3cbe, 0x48b5881f,
+0x3f4b9e2f, 0x18abb452, 0x2dee35f9, 0x79c9a085,
+0x0e3740d9, 0x95be5a93, 0xa46e0a24, 0xa19228db,
+0xf9a6d8d5, 0x260158f3, 0x43742638, 0x86f3e7b1,
+0x53a873c7, 0x4c3bbde4, 0x3a125a19, 0x183be282,
+0xd5d472eb, 0x4a9c635d, 0xe49e80c9, 0xa2c6661d,
+0x4967c618, 0xac9daf4b, 0x4919131a, 0x369f78eb,
+0x9bde7c9c, 0x553d5d0b, 0xc59a73d1, 0xff837337,
+0xe5ec7273, 0x1c8599b4, 0x696dc179, 0x9815ee07,
+0xe4df1239, 0x38e1c469, 0x6b794569, 0xa032785e,
+0x1acc0925, 0xf536cdd6, 0xebc5c6c2, 0x2a5d11d3,
+0x04a03d39, 0x633bced1, 0xa2001784, 0xf78c6b48,
+0xe072c5a1, 0xb1eaa433, 0xd7ced3b6, 0xf2c07440,
+0x4ffd6e7b, 0xaf2b878b, 0x60d7bc8e, 0x2b89dc5c,
+0xe117be9e, 0xc8ea7f6a, 0x865bbc9c, 0x304e977a,
+0x25a5d74b, 0x49a6fbec, 0xc0470ff4, 0xd83890fa,
+0x58f22c45, 0x077790b4, 0xd6402b4e, 0x719eaf0a,
+0x8ab72534, 0xec1a1894, 0x81f797c3, 0x1ecf65ab,
+0x37fe8f9e, 0x9481c873, 0x744d691b, 0xd9a6d1d4,
+0x6ee7a90e, 0x5bdc7a57, 0xc560c85f, 0x75124495,
+0x134501fe, 0x2fbdea57, 0xc1fe407f, 0x36828ba0,
+0x3da4c8d7, 0xa0006170, 0x81a4577d, 0xdc8e8a44,
+0xfc94a762, 0xe9b6be77, 0x7d7c04f7, 0x29c8276b,
+0xaa12fb03, 0xa6d27825, 0x9922dd69, 0x0e178d6e,
+0x449c8109, 0x4c827048, 0x35d3f205, 0x538eafc3,
+0x8bf248f1, 0x3130b9ec, 0x27a6b08d, 0xfef0100b,
+0xbcc85298, 0x2080ecdc, 0x39fdfb05, 0x62f7c480,
+0x19de60a6, 0xe2204f0f, 0x39ca59ea, 0xabdc7f01,
+0x81f5067b, 0x215857e5, 0x1b9b044f, 0x55db132d,
+0x716b8212, 0x81c3acbe, 0xdff0c9a1, 0xc60ad938,
+0xc8facc32, 0xaf6a82c0, 0x8018ee73, 0x0f722d8d,
+0x7ab0bbab, 0x06f44c6d, 0xc9bce017, 0xef88fba0,
+0xc65c84ec, 0xaec583f2, 0x9d2aca45, 0xd9836e2b,
+0xa4cb385c, 0xf59cd694, 0x409f5465, 0x37ce2de9,
+0x5366f8ab, 0x460fe096, 0x476cbd07, 0xf42481db,
+0xddba009f, 0xc679613a, 0x7165e0ed, 0x212ba7bb,
+0xaeea5527, 0x75397d7d, 0x368e0b80, 0xf0a1c5d4,
+0xe2e7a01f, 0x223b6d47, 0x0b006f6f, 0x5f42f904,
+0x76cb0e41, 0x4ff6b0ab, 0x90683eee, 0xc5f01511,
+0x11b563f0, 0x13a0b7f4, 0x247e667e, 0xd11bf6ea,
+0x285d4466, 0xd2dbfde5, 0x7b73744e, 0x8234b88d,
+0xd9c2a4a5, 0xf6efab9f, 0x2808dde0, 0x7655864b,
+0xa1b20c4f, 0x1d6ba18a, 0xc79a70c0, 0x7bf27476,
+0x9083f611, 0x8d9c7045, 0x6c0a8ca2, 0x1860df39,
+0xeb8e513b, 0x9adf5af9, 0x3a39fd75, 0x2c2d578f,
+0x0040c101, 0xf24719c2, 0xf7438575, 0xc642fa2d,
+0x195d6265, 0xb0f5f6d7, 0x9baed4fe, 0x496e9348,
+0x12f8158c, 0x20840886, 0xcb0d9354, 0xa2f7e0e8,
+0xfa4b7005, 0xc919bf15, 0xe8b19712, 0x5223fa2b,
+0x0a1435d4, 0xbd9daf74, 0x998a2d38, 0xa90eceb8,
+0x2796c980, 0x9ff72c53, 0x052fc633, 0x67165b0c,
+0x98f4291d, 0x4ccfa97c, 0xc0911676, 0x5d7233ad,
+0x57efc358, 0xe82361f5, 0x6cdcb7d8, 0x20288c6f,
+0x4bf05857, 0x59cc64ec, 0x984f354a, 0xdd1fa6d4,
+0x6fecf3ae, 0x6b22cbf5, 0x4aa15f77, 0xf306d041,
+0xed945e46, 0xcd9fe0b9, 0x234f4ae8, 0xc6fd791e,
+0xecd580cd, 0xe3de77ac, 0xa1031368, 0x15774eb8,
+0xa89a83a5, 0x67066915, 0xd73f2dee, 0xeeed86fe,
+0x714221a8, 0x48fa6cc3, 0x98f9e936, 0xc362fc00,
+0xc0d792c2, 0x751cc992, 0x4ee2902c, 0xb6f3648b,
+0xc766b9c2, 0xcc146335, 0x7870d73e, 0xc2e331e9,
+0x3a06414e, 0x43fec1c1, 0x8a69cc7c, 0x241be529,
+0x6697c6a9, 0x50bdb278, 0x2bd31bc9, 0x284d0b68,
+0x4c4f6fd7, 0x3d309a3c, 0x3f44ae0d, 0x3d5f323e,
+0x1018208b, 0x64eeebd4, 0xbf940e84, 0x1bdeb048,
+0x8959ce21, 0xb3e30da5, 0x086d9c68, 0x6e554b51,
+0xf4796046, 0x6a194705, 0x77d86ae8, 0xb23fe0cd,
+0xdfc1e29b, 0x53e92324, 0xbe41b2bd, 0xfaa02c03,
+0xe0362c1e, 0x7dbc10ba, 0x491d2567, 0xa44c023e,
+0x47c5f3f8, 0xdaa509f7, 0x1ee4214c, 0x40297c03,
+0x8cd29257, 0x8100c5ce, 0x481a3303, 0x93c360da,
+0xae1b0e83, 0x00eb3656, 0x5ff0fa97, 0xddcf7a1d,
+0x7c8c47fc, 0xbe3e8645, 0x450a395e, 0x18686d02,
+0xbfc53cdf, 0xaf084ade, 0xfc288cd9, 0xbb285f9f,
+0xddaf6201, 0xa40183d6, 0x41500319, 0x7e9e2a92,
+0xa5332190, 0xfda7abf6, 0x98be91ad, 0x76b15b7f,
+0x2db9446f, 0x1a60d2e2, 0x193e376c, 0x4932c9ac,
+0xeb87058a, 0x17a19742, 0x021df546, 0xde353932,
+0x795d5cf4, 0x86d450fb, 0xf660d67f, 0x6493b35a,
+0x174fc138, 0x3e98a209, 0x3b7d5903, 0x21684400,
+0x426ec5a9, 0xbebf63dc, 0xaab0f029, 0xc22dddae,
+0x4f306545, 0x4759cf34, 0x356b6f0c, 0x349884c1,
+0xaca3058a, 0x5e76e9dd, 0x806b7e27, 0x9cef8c14,
+0x451f90d5, 0xee50a4c5, 0x3a994015, 0x87d3cbc2,
+0x0bf9ef61, 0x3da7d552, 0xe9a5e121, 0x050a61da,
+0x6853fbb8, 0xd8420180, 0xf3f7036e, 0xe6ecb9ab,
+0xf336fe6d, 0x82deb26b, 0x56afafb0, 0x7b4cd669,
diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c
new file mode 100644
index 0000000000..18a1327633
--- /dev/null
+++ b/src/cpu/intel/haswell/microcode_blob.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+unsigned microcode[] = {
+#include "microcode_blob.h"
+};
+
diff --git a/src/cpu/intel/haswell/microcode_blob.h b/src/cpu/intel/haswell/microcode_blob.h
new file mode 100644
index 0000000000..1752e73e32
--- /dev/null
+++ b/src/cpu/intel/haswell/microcode_blob.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "microcode-M32306c1_ffff000d.h"
+#include "microcode-M32306c2_ffff0003.h"
+#include "microcode-M3240660_ffff000b.h"
+#include "microcode-M7240650_ffff0007.h"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
author	Aaron Durbin <adurbin@chromium.org>	2012-10-30 09:03:43 -0500
committer	Ronald G. Minnich <rminnich@gmail.com>	2013-03-14 01:44:40 +0100
commit	76c3700f02f79b49fec30d6ef18d336f122cbf50 (patch)
tree	cb1c750ef3946e2ae462e1847ec89946579274b2 /src/cpu/intel
parent	cc86e63e835ab0bceb62215460a13266a791cdd3 (diff)
download	coreboot-76c3700f02f79b49fec30d6ef18d336f122cbf50.tar.xz