summaryrefslogtreecommitdiff
path: root/src/cpu/intel
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2018-04-10 15:18:38 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-01-23 14:49:57 +0000
commit84fdda381224f0371e27ef3f0ad77ee1103cb05a (patch)
tree08aa40dd49e214fe0fd05b7960ba3b3c00e55ccb /src/cpu/intel
parentc82950bf79285fa838b6fbaf019a5638316ba053 (diff)
downloadcoreboot-84fdda381224f0371e27ef3f0ad77ee1103cb05a.tar.xz
nb/intel/pineview: Use parallel MP init
Remove guards around CPU code on which all platforms use parallel MP init code. This removes the option to disable HT siblings. Tested on Foxconn D41S. Change-Id: I89f7d514d75fe933c3a8858da37004419189674b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25602 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/model_106cx/model_106cx_init.c17
1 files changed, 0 insertions, 17 deletions
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 24a9ad29f6..75e110683e 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -17,12 +17,9 @@
#include <device/device.h>
#include <string.h>
#include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
-#include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h>
-#include <cpu/intel/hyperthreading.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/common/common.h>
@@ -84,20 +81,10 @@ static void model_106cx_init(struct device *cpu)
/* Turn on caching if we haven't already */
x86_enable_cache();
- /* Update the microcode */
- if (!IS_ENABLED(CONFIG_PARALLEL_MP))
- intel_update_microcode_from_cbfs();
-
/* Print processor name */
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
- /* Setup MTRRs */
- if (!IS_ENABLED(CONFIG_PARALLEL_MP)) {
- x86_setup_mtrrs();
- x86_mtrr_check();
- }
-
/* Enable the local CPU APICs */
setup_lapic();
@@ -111,10 +98,6 @@ static void model_106cx_init(struct device *cpu)
configure_misc();
/* TODO: PIC thermal sensor control */
-
- /* Start up my CPU siblings */
- if (!IS_ENABLED(CONFIG_PARALLEL_MP))
- intel_sibling_init(cpu);
}
static struct device_operations cpu_dev_ops = {