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authorPatrick Rudolph <patrick.rudolph@9elements.com>2019-09-26 10:26:49 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-10-01 15:10:16 +0000
commit6e079dc120a4aa95a25cfe536d4b1acd178918fd (patch)
treec8b1d76e5dd361964389c0f628b162102e72add1 /src/cpu/intel
parent5adbc767f66224e617b6c8204a868542b8010999 (diff)
downloadcoreboot-6e079dc120a4aa95a25cfe536d4b1acd178918fd.tar.xz
cpu/intel/common: Move intel_ht_sibling() to common folder
Make intel_ht_sibling() available on all platforms. Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked. Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/Makefile.inc2
-rw-r--r--src/cpu/intel/common/Kconfig3
-rw-r--r--src/cpu/intel/common/Makefile.inc3
-rw-r--r--src/cpu/intel/common/common.h7
-rw-r--r--src/cpu/intel/common/hyperthreading.c45
-rw-r--r--src/cpu/intel/fsp_model_406dx/Makefile.inc1
-rw-r--r--src/cpu/intel/haswell/Makefile.inc1
-rw-r--r--src/cpu/intel/hyperthreading/intel_sibling.c24
-rw-r--r--src/cpu/intel/model_1067x/Makefile.inc1
-rw-r--r--src/cpu/intel/model_106cx/Makefile.inc1
-rw-r--r--src/cpu/intel/model_2065x/Makefile.inc1
-rw-r--r--src/cpu/intel/model_206ax/Makefile.inc1
-rw-r--r--src/cpu/intel/model_f2x/Kconfig2
-rw-r--r--src/cpu/intel/model_f2x/model_f2x_init.c1
-rw-r--r--src/cpu/intel/model_f3x/Kconfig2
-rw-r--r--src/cpu/intel/model_f3x/model_f3x_init.c1
16 files changed, 65 insertions, 31 deletions
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 3f897407cf..484e241312 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -16,3 +16,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx
subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775
+
+subdirs-y += common
diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig
index 4074d8cc66..4fa3affb55 100644
--- a/src/cpu/intel/common/Kconfig
+++ b/src/cpu/intel/common/Kconfig
@@ -22,4 +22,7 @@ config SET_IA32_FC_LOCK_BIT
config CPU_INTEL_COMMON_TIMEBASE
bool
+config CPU_INTEL_COMMON_HYPERTHREADING
+ bool
+
endif
diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc
index c38e81c380..161201244c 100644
--- a/src/cpu/intel/common/Makefile.inc
+++ b/src/cpu/intel/common/Makefile.inc
@@ -1,4 +1,5 @@
-ramstage-y += common_init.c
+ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
+ramstage-$(CONFIG_CPU_INTEL_COMMON_HYPERTHREADING) += hyperthreading.c
ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y)
bootblock-y += fsb.c
diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h
index b9ac0566c6..f6b8e57ffd 100644
--- a/src/cpu/intel/common/common.h
+++ b/src/cpu/intel/common/common.h
@@ -15,6 +15,8 @@
#ifndef _CPU_INTEL_COMMON_H
#define _CPU_INTEL_COMMON_H
+#include <stdint.h>
+
void set_vmx_and_lock(void);
void set_feature_ctrl_vmx(void);
void set_feature_ctrl_lock(void);
@@ -27,4 +29,9 @@ void set_feature_ctrl_lock(void);
struct cppc_config;
void cpu_init_cppc_config(struct cppc_config *config, u32 version);
+/*
+ * Returns true if it's not thread 0 on a hyperthreading enabled core.
+ */
+bool intel_ht_sibling(void);
+
#endif
diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c
new file mode 100644
index 0000000000..4caf49e5b6
--- /dev/null
+++ b/src/cpu/intel/common/hyperthreading.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/common/common.h>
+#include <arch/cpu.h>
+
+/*
+ * Return true if running thread does not have the smallest lapic ID
+ * within a CPU core.
+ */
+bool intel_ht_sibling(void)
+{
+ struct cpuid_result result;
+ unsigned int core_ids, apic_ids, threads;
+
+ /* Is Hyper-Threading supported */
+ if (!(cpuid_edx(1) & CPUID_FEAURE_HTT))
+ return false;
+
+ apic_ids = 1;
+ if (cpuid_eax(0) >= 1)
+ apic_ids = (cpuid_ebx(1) >> 16) & 0xff;
+ if (apic_ids == 0)
+ apic_ids = 1;
+
+ core_ids = 1;
+ if (cpuid_eax(0) >= 4) {
+ result = cpuid_ext(4, 0);
+ core_ids += (result.eax >> 26) & 0x3f;
+ }
+
+ threads = (apic_ids / core_ids);
+ return !!(lapicid() & (threads - 1));
+}
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index d7fb4a886c..a3ebe3da06 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -13,7 +13,6 @@
ramstage-y += model_406dx_init.c
subdirs-y += ../../x86/name
-subdirs-y += ../common
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index 7661a4e2d8..aebeed497a 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -21,7 +21,6 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../turbo
-subdirs-y += ../common
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*)
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*)
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index 3c3e53a839..f5bcc87a10 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -25,30 +25,6 @@
static int first_time = 1;
static int disable_siblings = !CONFIG(LOGICAL_CPUS);
-/* Return true if running thread does not have the smallest lapic ID
- * within a CPU core.
- */
-int intel_ht_sibling(void)
-{
- unsigned int core_ids, apic_ids, threads;
-
- apic_ids = 1;
- if (cpuid_eax(0) >= 1)
- apic_ids = (cpuid_ebx(1) >> 16) & 0xff;
- if (apic_ids < 1)
- apic_ids = 1;
-
- core_ids = 1;
- if (cpuid_eax(0) >= 4) {
- struct cpuid_result result;
- result = cpuid_ext(4, 0);
- core_ids += (result.eax >> 26) & 0x3f;
- }
-
- threads = (apic_ids / core_ids);
- return !!(lapicid() & (threads-1));
-}
-
void intel_sibling_init(struct device *cpu)
{
unsigned int i, siblings;
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index 743e780a36..545f04de72 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,7 +1,6 @@
ramstage-y += model_1067x_init.c
ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c
subdirs-y += ../../x86/name
-subdirs-y += ../common
subdirs-y += ../smm/gen1
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*)
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 6701e6fc18..6d8414ec16 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -1,6 +1,5 @@
ramstage-y += model_106cx_init.c
subdirs-y += ../../x86/name
-subdirs-y += ../common
subdirs-y += ../smm/gen1
ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 4f6d3c2fd8..dde4234521 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -8,7 +8,6 @@ subdirs-y += ../../intel/turbo
subdirs-y += ../../intel/microcode
subdirs-y += ../../x86/smm
subdirs-y += ../smm/gen1
-subdirs-y += ../common
ramstage-y += acpi.c
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index d19d860304..391d126e77 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -1,7 +1,6 @@
ramstage-y += model_206ax_init.c
subdirs-y += ../../x86/name
subdirs-y += ../smm/gen1
-subdirs-y += ../common
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig
index 9e70775650..dcf94415d0 100644
--- a/src/cpu/intel/model_f2x/Kconfig
+++ b/src/cpu/intel/model_f2x/Kconfig
@@ -7,3 +7,5 @@ config CPU_INTEL_MODEL_F2X
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS
select SMM_ASEG
+ select CPU_INTEL_COMMON
+ select CPU_INTEL_COMMON_HYPERTHREADING
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index e759a43dc0..04710a9e68 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -17,6 +17,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/hyperthreading.h>
+#include <cpu/intel/common/common.h>
#include <cpu/x86/cache.h>
static void model_f2x_init(struct device *cpu)
diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig
index 7eaa820772..9a5e2a1caf 100644
--- a/src/cpu/intel/model_f3x/Kconfig
+++ b/src/cpu/intel/model_f3x/Kconfig
@@ -6,3 +6,5 @@ config CPU_INTEL_MODEL_F3X
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS
+ select CPU_INTEL_COMMON
+ select CPU_INTEL_COMMON_HYPERTHREADING
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index d348df6c82..48e3872225 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -17,6 +17,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/hyperthreading.h>
+#include <cpu/intel/common/common.h>
#include <cpu/x86/cache.h>
static void model_f3x_init(struct device *cpu)