summaryrefslogtreecommitdiff
path: root/src/cpu/intel
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2019-11-22 21:01:30 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-25 09:17:38 +0000
commitc05b1a66b320ab0341aae16c217316bec4092f5e (patch)
treeb85eb2b6c48ddb3c38604a55468e7f3608741801 /src/cpu/intel
parent689256797e0dc157046888f83bf64ae410df7f14 (diff)
downloadcoreboot-c05b1a66b320ab0341aae16c217316bec4092f5e.tar.xz
Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbol
The romcc bootblock will be deprecated soon and most platforms use C_ENVIRONMENT_BOOTBLOCK already. This patch drops the CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK where needed. Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/car/non-evict/cache_as_ram.S2
-rw-r--r--src/cpu/intel/car/p3/cache_as_ram.S2
-rw-r--r--src/cpu/intel/car/romstage.c4
-rw-r--r--src/cpu/intel/microcode/Kconfig2
-rw-r--r--src/cpu/intel/model_206ax/Kconfig1
-rw-r--r--src/cpu/intel/slot_1/Kconfig1
-rw-r--r--src/cpu/intel/socket_mPGA604/Kconfig1
7 files changed, 6 insertions, 7 deletions
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index cd6972062c..5a668c42df 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -29,7 +29,7 @@ _cache_as_ram_setup:
bootblock_pre_c_entry:
-#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(ROMCC_BOOTBLOCK)
movl $cache_as_ram, %esp /* return address */
jmp check_mtrr /* Check if CPU properly reset */
#endif
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
index a3487dbe34..23df701e08 100644
--- a/src/cpu/intel/car/p3/cache_as_ram.S
+++ b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -18,7 +18,7 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(ROMCC_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 9d196356e3..1f8eb9a10e 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -71,8 +71,8 @@ static void romstage_main(unsigned long bist)
/* We do not return here. */
}
-#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
-/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
+#if CONFIG(ROMCC_BOOTBLOCK)
+/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK
* keeping changes in cache_as_ram.S easy to manage.
*/
asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig
index b78389215d..73afe0bb45 100644
--- a/src/cpu/intel/microcode/Kconfig
+++ b/src/cpu/intel/microcode/Kconfig
@@ -1,7 +1,7 @@
config MICROCODE_UPDATE_PRE_RAM
bool
depends on SUPPORT_CPU_UCODE_IN_CBFS
- default y if C_ENVIRONMENT_BOOTBLOCK
+ default y if !ROMCC_BOOTBLOCK
help
Select this option if you want to update the microcode
during the cache as ram setup.
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index f316329552..e31260588e 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -21,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON_TIMEBASE
select PARALLEL_MP
select NO_FIXED_XIP_ROM_SIZE
- select C_ENVIRONMENT_BOOTBLOCK
config SMM_TSEG_SIZE
hex
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index 10001bdc5f..00af79a440 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -27,6 +27,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select UNKNOWN_TSC_RATE
+ select ROMCC_BOOTBLOCK
config DCACHE_RAM_BASE
hex
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index a2ebeb2325..176ae9e08a 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -11,7 +11,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select SIPI_VECTOR_IN_ROM
- select C_ENVIRONMENT_BOOTBLOCK
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE