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authorUwe Hermann <uwe@hermann-uwe.de>2010-10-01 21:46:04 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-10-01 21:46:04 +0000
commitdd8367006cf1a400384ff7076379bb53c6abea8a (patch)
tree9e6b74a79611549266680071d3fa72558063d5f5 /src/cpu/intel
parent2ba2b553b5ec01dced1ebadfa086c926f441f754 (diff)
downloadcoreboot-dd8367006cf1a400384ff7076379bb53c6abea8a.tar.xz
Factor out common CAR asm snippets.
This makes the CAR implementations a lot more readable, shorter and easier to follow, and also reduces the amount of uselessly duplicated code. For example there are more than 12 open-coded "enable cache" instances spread all over the place (and 12 "disable cache" ones), multiple "enable mtrr", "save BIST", "restore BIST", etc. etc. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/car/cache_as_ram.inc22
-rw-r--r--src/cpu/intel/model_106cx/cache_as_ram.inc61
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc61
-rw-r--r--src/cpu/intel/model_6fx/cache_as_ram.inc61
4 files changed, 51 insertions, 154 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 8491d86db2..6ff0287186 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -21,6 +21,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <cpu/x86/car.h>
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic_def.h>
@@ -28,8 +29,7 @@
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
- /* Save the BIST result. */
- movl %eax, %ebp
+ save_bist_result()
CacheAsRam:
/* Check whether the processor has HT capability. */
@@ -231,10 +231,7 @@ clear_fixed_var_mtrr_out:
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
- /* Enable cache. */
- movl %cr0, %eax
- andl $(~((1 << 30) | (1 << 29))), %eax
- movl %eax, %cr0
+ enable_cache()
/* Read the range with lodsl. */
movl $CacheBase, %esi
@@ -295,8 +292,7 @@ clear_fixed_var_mtrr_out:
movl $(CacheBase + CacheSize - 4), %eax
movl %eax, %esp
lout:
- /* Restore the BIST result. */
- movl %ebp, %eax
+ restore_bist_result()
/* We need to set EBP? No need. */
movl %esp, %ebp
@@ -305,10 +301,7 @@ lout:
/* We don't need CAR from now on. */
- /* Disable cache. */
- movl %cr0, %eax
- orl $(1 << 30), %eax
- movl %eax, %cr0
+ disable_cache()
/* Clear sth. */
movl $MTRRfix4K_C8000_MSR, %ecx
@@ -330,10 +323,7 @@ lout:
movl $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */
wrmsr
- /* Enable cache. */
- movl %cr0, %eax
- andl $(~((1 << 30) | (1 << 29))), %eax
- movl %eax, %cr0
+ enable_cache();
/* Clear boot_complete flag. */
xorl %ebp, %ebp
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index 87b465e928..03e0c2671c 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -18,14 +18,14 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <cpu/x86/car.h>
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
- /* Save the BIST result. */
- movl %eax, %ebp
+ save_bist_result()
cache_as_ram:
post_code(0x20)
@@ -66,19 +66,12 @@ clear_mtrrs:
xorl %edx, %edx
wrmsr
- /* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- orl $(1 << 11), %eax
- wrmsr
+ enable_mtrr()
- /* Enable L2 cache. */
- movl $0x11e, %ecx
- rdmsr
- orl $(1 << 8), %eax
- wrmsr
+ enable_l2_cache()
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+ /* TODO: enable_cache()? But that doesn't have "invd". */
movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax
invd
@@ -93,9 +86,7 @@ clear_mtrrs:
rep stosl
/* Enable Cache-as-RAM mode by disabling cache. */
- movl %cr0, %eax
- orl $(1 << 30), %eax
- movl %eax, %cr0
+ disable_cache()
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* Enable cache for our code in Flash because we do XIP here */
@@ -116,10 +107,7 @@ clear_mtrrs:
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
- /* Enable cache. */
- movl %cr0, %eax
- andl $(~((1 << 30) | (1 << 29))), %eax
- movl %eax, %cr0
+ enable_cache()
/* Set up the stack pointer. */
#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
@@ -130,8 +118,8 @@ clear_mtrrs:
#endif
movl %eax, %esp
- /* Restore the BIST result. */
- movl %ebp, %eax
+ restore_bist_result()
+
movl %esp, %ebp
pushl %eax
@@ -144,18 +132,11 @@ clear_mtrrs:
post_code(0x30)
- /* Disable cache. */
- movl %cr0, %eax
- orl $(1 << 30), %eax
- movl %eax, %cr0
+ disable_cache()
post_code(0x31)
- /* Disable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- andl $(~(1 << 11)), %eax
- wrmsr
+ disable_mtrr()
post_code(0x31)
@@ -175,17 +156,11 @@ clear_mtrrs:
post_code(0x33)
- /* Enable cache. */
- movl %cr0, %eax
- andl $~((1 << 30) | (1 << 29)), %eax
- movl %eax, %cr0
+ enable_cache()
post_code(0x36)
- /* Disable cache. */
- movl %cr0, %eax
- orl $(1 << 30), %eax
- movl %eax, %cr0
+ disable_cache()
post_code(0x38)
@@ -202,17 +177,11 @@ clear_mtrrs:
post_code(0x39)
/* And enable cache again after setting MTRRs. */
- movl %cr0, %eax
- andl $~((1 << 30) | (1 << 29)), %eax
- movl %eax, %cr0
+ enable_cache()
post_code(0x3a)
- /* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- orl $(1 << 11), %eax
- wrmsr
+ enable_mtrr()
post_code(0x3b)
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index dbc7cdc583..6d88e7b8e5 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -18,14 +18,14 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <cpu/x86/car.h>
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
- /* Save the BIST result. */
- movl %eax, %ebp
+ save_bist_result()
cache_as_ram:
post_code(0x20)
@@ -66,19 +66,12 @@ clear_mtrrs:
movl $0x0000000f, %edx
wrmsr
- /* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- orl $(1 << 11), %eax
- wrmsr
+ enable_mtrr()
- /* Enable L2 cache. */
- movl $0x11e, %ecx
- rdmsr
- orl $(1 << 8), %eax
- wrmsr
+ enable_l2_cache()
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+ /* TODO: enable_cache()? But that doesn't have "invd". */
movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax
invd
@@ -93,9 +86,7 @@ clear_mtrrs:
rep stosl
/* Enable Cache-as-RAM mode by disabling cache. */
- movl %cr0, %eax
- orl $(1 << 30), %eax
- movl %eax, %cr0
+ disable_cache()
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* Enable cache for our code in Flash because we do XIP here */
@@ -116,10 +107,7 @@ clear_mtrrs:
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
- /* Enable cache. */
- movl %cr0, %eax
- andl $(~((1 << 30) | (1 << 29))), %eax
- movl %eax, %cr0
+ enable_cache()
/* Set up the stack pointer. */
#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
@@ -130,8 +118,8 @@ clear_mtrrs:
#endif
movl %eax, %esp
- /* Restore the BIST result. */
- movl %ebp, %eax
+ restore_bist_result()
+
movl %esp, %ebp
pushl %eax
@@ -144,18 +132,11 @@ clear_mtrrs:
post_code(0x30)
- /* Disable cache. */
- movl %cr0, %eax
- orl $(1 << 30), %eax
- movl %eax, %cr0
+ disable_cache()
post_code(0x31)
- /* Disable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- andl $(~(1 << 11)), %eax
- wrmsr
+ disable_mtrr()
post_code(0x31)
@@ -175,17 +156,11 @@ clear_mtrrs:
post_code(0x33)
- /* Enable cache. */
- movl %cr0, %eax
- andl $~((1 << 30) | (1 << 29)), %eax
- movl %eax, %cr0
+ enable_cache()
post_code(0x36)
- /* Disable cache. */
- movl %cr0, %eax
- orl $(1 << 30), %eax
- movl %eax, %cr0
+ disable_cache()
post_code(0x38)
@@ -202,17 +177,11 @@ clear_mtrrs:
post_code(0x39)
/* And enable cache again after setting MTRRs. */
- movl %cr0, %eax
- andl $~((1 << 30) | (1 << 29)), %eax
- movl %eax, %cr0
+ enable_cache()
post_code(0x3a)
- /* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- orl $(1 << 11), %eax
- wrmsr
+ enable_mtrr()
post_code(0x3b)
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 74314c2571..526d24520d 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -18,14 +18,14 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <cpu/x86/car.h>
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
- /* Save the BIST result. */
- movl %eax, %ebp
+ save_bist_result()
cache_as_ram:
post_code(0x20)
@@ -73,19 +73,12 @@ clear_mtrrs:
movl $0x0000000f, %edx
wrmsr
- /* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- orl $(1 << 11), %eax
- wrmsr
+ enable_mtrr()
- /* Enable L2 cache. */
- movl $0x11e, %ecx
- rdmsr
- orl $(1 << 8), %eax
- wrmsr
+ enable_l2_cache()
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+ /* TODO: enable_cache()? But that doesn't have "invd". */
movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax
invd
@@ -100,9 +93,7 @@ clear_mtrrs:
rep stosl
/* Enable Cache-as-RAM mode by disabling cache. */
- movl %cr0, %eax
- orl $(1 << 30), %eax
- movl %eax, %cr0
+ disable_cache()
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* Enable cache for our code in Flash because we do XIP here */
@@ -123,10 +114,7 @@ clear_mtrrs:
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
- /* Enable cache. */
- movl %cr0, %eax
- andl $(~((1 << 30) | (1 << 29))), %eax
- movl %eax, %cr0
+ enable_cache()
/* Set up the stack pointer. */
#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
@@ -137,8 +125,8 @@ clear_mtrrs:
#endif
movl %eax, %esp
- /* Restore the BIST result. */
- movl %ebp, %eax
+ restore_bist_result()
+
movl %esp, %ebp
pushl %eax
@@ -151,18 +139,11 @@ clear_mtrrs:
post_code(0x30)
- /* Disable cache. */
- movl %cr0, %eax
- orl $(1 << 30), %eax
- movl %eax, %cr0
+ disable_cache()
post_code(0x31)
- /* Disable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- andl $(~(1 << 11)), %eax
- wrmsr
+ disable_mtrr()
post_code(0x31)
@@ -182,17 +163,11 @@ clear_mtrrs:
post_code(0x33)
- /* Enable cache. */
- movl %cr0, %eax
- andl $~((1 << 30) | (1 << 29)), %eax
- movl %eax, %cr0
+ enable_cache()
post_code(0x36)
- /* Disable cache. */
- movl %cr0, %eax
- orl $(1 << 30), %eax
- movl %eax, %cr0
+ disable_cache()
post_code(0x38)
@@ -209,17 +184,11 @@ clear_mtrrs:
post_code(0x39)
/* And enable cache again after setting MTRRs. */
- movl %cr0, %eax
- andl $~((1 << 30) | (1 << 29)), %eax
- movl %eax, %cr0
+ enable_cache()
post_code(0x3a)
- /* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- orl $(1 << 11), %eax
- wrmsr
+ enable_mtrr()
post_code(0x3b)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 21:15:02 +0000