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authorEric Biederman <ebiederm@xmission.com>2004-10-30 08:05:41 +0000
committerEric Biederman <ebiederm@xmission.com>2004-10-30 08:05:41 +0000
commitf8a2dddb573faef41ad43ee111d91d4c5259ad59 (patch)
tree3606ac56f585bce51868b8a5388bf9d0bb4561b9 /src/cpu/intel
parent0afcba7a3d0e7dc22818ecdfd79230f5fb987f0d (diff)
downloadcoreboot-f8a2dddb573faef41ad43ee111d91d4c5259ad59.tar.xz
- To reduce confuse rename the parts of linuxbios bios that run from
ram linuxbios_ram instead of linuxbios_c and linuxbios_payload... - Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86 - ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB. - Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work. - Start using romcc's built in preprocessor (This will simplify header compiler checks) - Add helper functions for examining all of the resources - Remove debug strings from chip.h - Add llshell to src/arch/i386/llshell (Sometime later I can try it...) - Add the ability to catch exceptions on x86 - Add gdb_stub support to x86 - Removed old cpu options - Added an option so we can detect movnti support - Remove some duplicate definitions from pci_ids.h - Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic - Minor romcc bug fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/model_f0x/Config.lb2
-rw-r--r--src/cpu/intel/model_f1x/Config.lb2
-rw-r--r--src/cpu/intel/model_f2x/Config.lb2
-rw-r--r--src/cpu/intel/model_f3x/Config.lb2
4 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/intel/model_f0x/Config.lb b/src/cpu/intel/model_f0x/Config.lb
index 1e6126c3cc..2458c81c14 100644
--- a/src/cpu/intel/model_f0x/Config.lb
+++ b/src/cpu/intel/model_f0x/Config.lb
@@ -1,3 +1,5 @@
+uses HAVE_MOVNTI
+default HAVE_MOVNTI=1
dir /cpu/x86/tsc
dir /cpu/x86/mtrr
dir /cpu/x86/fpu
diff --git a/src/cpu/intel/model_f1x/Config.lb b/src/cpu/intel/model_f1x/Config.lb
index d318ee538d..5387d455f1 100644
--- a/src/cpu/intel/model_f1x/Config.lb
+++ b/src/cpu/intel/model_f1x/Config.lb
@@ -1,3 +1,5 @@
+uses HAVE_MOVNTI
+default HAVE_MOVNTI=1
dir /cpu/x86/tsc
dir /cpu/x86/mtrr
dir /cpu/x86/fpu
diff --git a/src/cpu/intel/model_f2x/Config.lb b/src/cpu/intel/model_f2x/Config.lb
index 10fe8b767b..ef9d095ac5 100644
--- a/src/cpu/intel/model_f2x/Config.lb
+++ b/src/cpu/intel/model_f2x/Config.lb
@@ -1,3 +1,5 @@
+uses HAVE_MOVNTI
+default HAVE_MOVNTI=1
dir /cpu/x86/tsc
dir /cpu/x86/mtrr
dir /cpu/x86/fpu
diff --git a/src/cpu/intel/model_f3x/Config.lb b/src/cpu/intel/model_f3x/Config.lb
index dc58d7df50..175ff58919 100644
--- a/src/cpu/intel/model_f3x/Config.lb
+++ b/src/cpu/intel/model_f3x/Config.lb
@@ -1,3 +1,5 @@
+uses HAVE_MOVNTI
+default HAVE_MOVNTI=1
dir /cpu/x86/tsc
dir /cpu/x86/mtrr
dir /cpu/x86/fpu