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authorAlexandru Gagniuc <mr.nuke.me@gmail.com>2012-07-20 00:11:21 -0500
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2012-09-05 03:40:47 +0200
commit00b579a4478431dbfcef154ec80f5aa7d08d6529 (patch)
tree10ebe6f9b87dbf6dfc0f05a830da48060dad4b41 /src/cpu/intel
parenteb1d39bac4d3638d41fc38274ae7a133d7b5c6f2 (diff)
downloadcoreboot-00b579a4478431dbfcef154ec80f5aa7d08d6529.tar.xz
buildsystem: Make CPU microcode updating more configurable
This patch aims to improve the microcode in CBFS handling that was brought by the last patches from Stefan and the Chromium team. Choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. MICROCODE_INCLUDE_PATH Kconfig variable is eliminated. Microcode is handled by a special class, cpu_microcode, as such: cpu_microcode-y += microcode_file.c MICROCODE_IN_CBFS should, in the future, be eliminated. Right now it is needed by intel microcode updating. Once all intel cpus are converted to cbfs updating, this variable can go away. These files are then compiled and assembled into a binary CBFS file. The advantage of doing it this way versus the current method is that 1) The rule is CPU-agnostic 2) Gives user more control over if and how to include microcode blobs 3) The rules for building the microcode binary are kept in src/cpu/Makefile.inc, and thus would not clobber the other makefiles, which are already overloaded and very difficult to navigate. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1245 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/microcode/Makefile.inc20
-rw-r--r--src/cpu/intel/microcode/microcode.c8
-rw-r--r--src/cpu/intel/model_206ax/Kconfig2
-rw-r--r--src/cpu/intel/model_206ax/Makefile.inc2
-rw-r--r--src/cpu/intel/model_206ax/microcode_blob.c (renamed from src/cpu/intel/microcode/microcode_blob.c)2
5 files changed, 13 insertions, 21 deletions
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
index f4d01020d1..22655c9532 100644
--- a/src/cpu/intel/microcode/Makefile.inc
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -1,15 +1,5 @@
-ramstage-y += microcode.c
-
-
-ifeq ($(CONFIG_MICROCODE_IN_CBFS),y)
-
-SRC_PATH = src/cpu/intel/microcode
-FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h
-$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c
- $(CC) $(FLAGS) -MMD -c -o $@ $<
-
-$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o
- objcopy -j .data -O binary $< $@
-
--include $(obj)/microcode_blob.d
-endif
+################################################################################
+## One small file with the awesome super-power of updating the cpu microcode
+## directly from CBFS. You have been WARNED!!!
+################################################################################
+ramstage-y += microcode.c \ No newline at end of file
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index e84bad9beb..a4471ca042 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -28,7 +28,7 @@
#include <cpu/x86/msr.h>
#include <cpu/intel/microcode.h>
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
#ifdef __PRE_RAM__
#include <arch/cbfs.h>
#else
@@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void)
return msr.hi;
}
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
static
#endif
void intel_update_microcode(const void *microcode_updates)
@@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates)
}
}
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
-#define MICROCODE_CBFS_FILE "microcode_blob.bin"
+#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
void intel_update_microcode_from_cbfs(void)
{
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 6635868453..5c543b88ba 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS
select SSE2
select UDELAY_LAPIC
select SMM_TSEG
- select MICROCODE_IN_CBFS
+ select CPU_MICROCODE_IN_CBFS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index e9b8e6df8e..6ab4840c48 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -5,4 +5,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+
cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/microcode/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
index 69238a9f77..c2538e8ede 100644
--- a/src/cpu/intel/microcode/microcode_blob.c
+++ b/src/cpu/intel/model_206ax/microcode_blob.c
@@ -18,5 +18,5 @@
*/
unsigned microcode[] = {
-#include <microcode_blob.h>
+#include "microcode_blob.h"
};