summaryrefslogtreecommitdiff
path: root/src/cpu/intel
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2019-01-11 23:56:51 +0100
committerArthur Heymans <arthur@aheymans.xyz>2019-01-15 11:38:01 +0000
commit19e7273ec2dc243b4089b9aeeaf7929ff5a20a34 (patch)
tree98894887d49e25e325f9d87eb9677e932d112400 /src/cpu/intel
parent0feaa85233c099b06f84d5a0e1d82575efdba56b (diff)
downloadcoreboot-19e7273ec2dc243b4089b9aeeaf7929ff5a20a34.tar.xz
cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup
Pineview CPUs support a non-eviction mode that ought to be used during cache as ram setup. This assumes that all atoms that need to set a special register to enable L2 cache are socketed and hence uses a static Kconfig option to set that MSR on affected CPUs. Tested on Foxconn D41S, still boots. Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30863 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/Kconfig1
-rw-r--r--src/cpu/intel/car/non-evict/Kconfig5
-rw-r--r--src/cpu/intel/car/non-evict/cache_as_ram.S13
-rw-r--r--src/cpu/intel/socket_FCBGA559/Kconfig3
-rw-r--r--src/cpu/intel/socket_FCBGA559/Makefile.inc4
5 files changed, 24 insertions, 2 deletions
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index f5d0ab9268..18f73b45d1 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -36,3 +36,4 @@ source src/cpu/intel/fit/Kconfig
source src/cpu/intel/turbo/Kconfig
source src/cpu/intel/common/Kconfig
source src/cpu/intel/microcode/Kconfig
+source src/cpu/intel/car/non-evict/Kconfig
diff --git a/src/cpu/intel/car/non-evict/Kconfig b/src/cpu/intel/car/non-evict/Kconfig
new file mode 100644
index 0000000000..faf13e704d
--- /dev/null
+++ b/src/cpu/intel/car/non-evict/Kconfig
@@ -0,0 +1,5 @@
+config CPU_HAS_L2_ENABLE_MSR
+ bool
+ help
+ Select this in Kconfig of CPU sockets/SOC where the CPU
+ has an MSR to enable the L2 CPU cache
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index d2beaa7d5a..3203159f40 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -24,6 +24,7 @@
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#define NoEvictMod_MSR 0x2e0
+#define BBL_CR_CTL3_MSR 0x11e
.global bootblock_pre_c_entry
@@ -133,6 +134,18 @@ addrsize_set_high:
orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
+#if IS_ENABLED(CONFIG_CPU_HAS_L2_ENABLE_MSR)
+ /*
+ * Enable the L2 cache. Currently this assumes that this
+ * only affect socketed CPU's for which this is always valid,
+ * hence the static preprocesser.
+ */
+ movl $BBL_CR_CTL3_MSR, %ecx
+ rdmsr
+ orl $0x100, %eax
+ wrmsr
+#endif
+
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig
index d1cc80f7bc..6566a01cf8 100644
--- a/src/cpu/intel/socket_FCBGA559/Kconfig
+++ b/src/cpu/intel/socket_FCBGA559/Kconfig
@@ -1,5 +1,7 @@
config CPU_INTEL_SOCKET_FCBGA559
bool
+ help
+ Select this socket on Intel Pineview
if CPU_INTEL_SOCKET_FCBGA559
@@ -8,6 +10,7 @@ config SOCKET_SPECIFIC_OPTIONS
select CPU_INTEL_MODEL_106CX
select MMX
select SSE
+ select CPU_HAS_L2_ENABLE_MSR
config DCACHE_RAM_BASE
hex
diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc
index 7993294a17..868f6e5608 100644
--- a/src/cpu/intel/socket_FCBGA559/Makefile.inc
+++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc
@@ -8,7 +8,7 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
-cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
-postcar-y += ../car/p4-netburst/exit_car.S
+cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
+postcar-y += ../car/non-evict/exit_car.S
romstage-y += ../car/romstage.c